CachePInterfacePRAMDriver.rose
Last edited by: Barth, July 3, 1984 4:41:42 pm PDT
Last edited by: Curry, January 29, 1985 9:29:42 pm PST
Imports BitOps, BitSwOps, CacheOps, Dragon;
Open BitOps, BitSwOps, Dragon;
CELLTYPE "PRAMDriver"
PORTS[
Timing and housekeeping interface
Vdd, Gnd<BOOL,
Buffered timing and housekeeping interface
nPhAb<BOOL,
RAM access
PBitsB, nPBitsB=SWITCH[132]-(Special XPhobic),
Internal processor interface
PDataI=INT[32],
PParityI=BOOL,
PRAMDriver interface
PRamRegSensePDataIB, PRamRegDrivePDataIB, PRamRegSensePBitsB, PRamRegDrivePBitsB<BOOL,
PRamRegParityOut>BOOL,
PAdr3031AB<INT[2]
]
State
PRAMReg: BitDWord,
PRAMRegParity: BOOL
EvalSimple
offset: CARDINAL ← ECFW[PAdr3031AB, 2, 0, 2];
IF PRamRegSensePDataIB THEN {
PRAMReg ← PDataI;
PRAMRegParity ← PParityI;
};
Assert[NOT MoreThanOneOf[PRamRegSensePDataIB, PRamRegSensePBitsB]];
Assert[NOT MoreThanOneOf[PRamRegDrivePDataIB, PRamRegDrivePBitsB]];
TRUSTED {
pbitd: SwitchMWord ← DESCRIPTOR[PBitsB];
npbitd: SwitchMWord ← DESCRIPTOR[nPBitsB];
CacheOps.DriveBus[pbitd, npbitd, PRamRegDrivePBitsB, offset, PRAMReg, PRAMRegParity];
IF NOT nPhAb THEN {
FOR j:CARDINAL IN [0..4) DO
SCDTS[BitDWordOnes, 32, 0, 32, pbitd, 132, j*32, 32, [[none, X], [drive, H]]];
SCDTS[BitDWordOnes, 32, 0, 32, npbitd, 132, j*32, 32, [[none, X], [drive, H]]];
ENDLOOP;
SCWTS[BitWordOnes, 16, 0, 4, pbitd, 132, 128, 4, [[none, X], [drive, H]]];
SCWTS[BitWordOnes, 16, 0, 4, npbitd, 132, 128, 4, [[none, X], [drive, H]]];
};
IF PRamRegSensePBitsB THEN {
FOR i:CARDINAL IN [0..32) DO
PRAMReg ← IBID[EBFS[pbitd, 132, (4*i)+offset], PRAMReg, 32, i];
ENDLOOP;
PRAMRegParity ← EBFS[pbitd, 132, 128+offset];
};
};
PRamRegParityOut ← CacheOps.Parity32[LOOPHOLE[PRAMReg]];
IF PRAMRegParity THEN PRamRegParityOut ← NOT PRamRegParityOut;
IF PRamRegDrivePDataIB THEN {
PDataI ← PRAMReg;
PParityI ← PRAMRegParity;
};
ENDCELLTYPE