CachePInterfacePRAMDriver.Mesa
created by RoseTranslate from CachePInterfacePRAMDriver.Rose of January 29, 1985 10:14:49 pm PST for curry.pa at January 29, 1985 10:15:39 pm PST
DIRECTORY
RoseTypes, RoseCreate, BitOps, BitSwOps, CacheOps, Dragon, SwitchTypes;
CachePInterfacePRAMDriver: CEDAR PROGRAM
IMPORTS RoseCreate, BitOps, BitSwOps, CacheOps, Dragon =
BEGIN OPEN
RoseTypes, BitOps, BitSwOps, Dragon;
Signal Type decls
RegisterCells: PROC =
BEGIN
[] ← RoseCreate.RegisterCellType[name: "PRAMDriver",
expandProc: NIL,
ioCreator: CreatePRAMDriverIO, initializer: InitializePRAMDriver,
evals: [EvalSimple: PRAMDriverEvalSimple],
blackBox: NIL, stateToo: NIL,
ports: CreatePRAMDriverPorts[],
drivePrototype: NEW [PRAMDriverDrive]];
END;
otherss: SymbolTable ← RoseCreate.GetOtherss["CachePInterfacePRAMDriver.pass"];
CreatePRAMDriverPorts: PROC RETURNS [ports: Ports] = {ports ← RoseCreate.PortsFromFile["CachePInterfacePRAMDriver.PRAMDriver.rosePorts"]};
PRAMDriverIORef: TYPE = REF PRAMDriverIORec;
PRAMDriverIORec: TYPE = MACHINE DEPENDENT RECORD [
fill0(0:0..14): [0..32767],
Vdd(0:15..15): BOOLEAN,
fill1(1:0..14): [0..32767],
Gnd(1:15..15): BOOLEAN,
fill2(2:0..14): [0..32767],
nPhAb(2:15..15): BOOLEAN,
PBitsB(3:0..2111): PACKED ARRAY [0 .. 131] OF SwitchTypes.SwitchVal,
nPBitsB(135:0..2111): PACKED ARRAY [0 .. 131] OF SwitchTypes.SwitchVal,
PDataI(267:0..31): ARRAY [0..2) OF CARDINAL,
fill6(269:0..14): [0..32767],
PParityI(269:15..15): BOOLEAN,
fill7(270:0..14): [0..32767],
PRamRegSensePDataIB(270:15..15): BOOLEAN,
fill8(271:0..14): [0..32767],
PRamRegDrivePDataIB(271:15..15): BOOLEAN,
fill9(272:0..14): [0..32767],
PRamRegSensePBitsB(272:15..15): BOOLEAN,
fill10(273:0..14): [0..32767],
PRamRegDrivePBitsB(273:15..15): BOOLEAN,
fill11(274:0..14): [0..32767],
PRamRegParityOut(274:15..15): BOOLEAN,
fill12(275:0..13): [0..16383],
PAdr3031AB(275:14..15): [0..3]];
port indices:
PRAMDriverPBitsBPortIndex: CARDINAL = 3;
PRAMDriverNPBitsBPortIndex: CARDINAL = 4;
PRAMDriverDrive: TYPE = MACHINE DEPENDENT RECORD [
fill0(0:0..14): [0 .. 32768),
Vdd(0:15..15): BOOLEAN,
fill1(1:0..14): [0 .. 32768),
Gnd(1:15..15): BOOLEAN,
fill2(2:0..14): [0 .. 32768),
nPhAb(2:15..15): BOOLEAN,
fill3(3:0..14): [0 .. 32768),
PBitsB(3:15..15): BOOLEAN,
fill4(4:0..14): [0 .. 32768),
nPBitsB(4:15..15): BOOLEAN,
fill5(5:0..14): [0 .. 32768),
PDataI(5:15..15): BOOLEAN,
fill6(6:0..14): [0 .. 32768),
PParityI(6:15..15): BOOLEAN,
fill7(7:0..14): [0 .. 32768),
PRamRegSensePDataIB(7:15..15): BOOLEAN,
fill8(8:0..14): [0 .. 32768),
PRamRegDrivePDataIB(8:15..15): BOOLEAN,
fill9(9:0..14): [0 .. 32768),
PRamRegSensePBitsB(9:15..15): BOOLEAN,
fill10(10:0..14): [0 .. 32768),
PRamRegDrivePBitsB(10:15..15): BOOLEAN,
fill11(11:0..14): [0 .. 32768),
PRamRegParityOut(11:15..15): BOOLEAN,
fill12(12:0..14): [0 .. 32768),
PAdr3031AB(12:15..15): BOOLEAN];
CreatePRAMDriverIO: PROC [cell: Cell] --IOCreator-- = {
cell.realCellStuff.switchIO ← NEW [PRAMDriverIORec];
cell.realCellStuff.newIO ← NEW [PRAMDriverIORec];
cell.realCellStuff.oldIO ← NEW [PRAMDriverIORec];
};
PRAMDriverStateRef: TYPE = REF PRAMDriverStateRec;
PRAMDriverStateRec: TYPE = RECORD [
PRAMReg: BitDWord,
PRAMRegParity: BOOL
];
InitializePRAMDriver: Initializer = {
IF leafily THEN
BEGIN
state: PRAMDriverStateRef ← NEW [PRAMDriverStateRec];
cell.realCellStuff.state ← state;
END;
};
PRAMDriverEvalSimple: CellProc =
BEGIN
sw: PRAMDriverIORef ← NARROW[cell.realCellStuff.switchIO];
newIO: PRAMDriverIORef ← NARROW[cell.realCellStuff.newIO];
state: PRAMDriverStateRef ← NARROW[cell.realCellStuff.state];
BEGIN OPEN newIO, state;
offset: CARDINAL ← ECFW[PAdr3031AB, 2, 0, 2];
IF PRamRegSensePDataIB THEN {
PRAMReg ← PDataI;
PRAMRegParity ← PParityI;
};
Assert[NOT MoreThanOneOf[PRamRegSensePDataIB, PRamRegSensePBitsB]];
Assert[NOT MoreThanOneOf[PRamRegDrivePDataIB, PRamRegDrivePBitsB]];
TRUSTED {
pbitd: SwitchMWord ← DESCRIPTOR[PBitsB];
npbitd: SwitchMWord ← DESCRIPTOR[nPBitsB];
CacheOps.DriveBus[pbitd, npbitd, PRamRegDrivePBitsB, offset, PRAMReg, PRAMRegParity];
IF NOT nPhAb THEN {
FOR j:CARDINAL IN [0..4) DO
SCDTS[BitDWordOnes, 32, 0, 32, pbitd, 132, j*32, 32, [[none, X], [drive, H]]];
SCDTS[BitDWordOnes, 32, 0, 32, npbitd, 132, j*32, 32, [[none, X], [drive, H]]];
ENDLOOP;
SCWTS[BitWordOnes, 16, 0, 4, pbitd, 132, 128, 4, [[none, X], [drive, H]]];
SCWTS[BitWordOnes, 16, 0, 4, npbitd, 132, 128, 4, [[none, X], [drive, H]]];
};
IF PRamRegSensePBitsB THEN {
FOR i:CARDINAL IN [0..32) DO
PRAMReg ← IBID[EBFS[pbitd, 132, (4*i)+offset], PRAMReg, 32, i];
ENDLOOP;
PRAMRegParity ← EBFS[pbitd, 132, 128+offset];
};
};
PRamRegParityOut ← CacheOps.Parity32[LOOPHOLE[PRAMReg]];
IF PRAMRegParity THEN PRamRegParityOut ← NOT PRamRegParityOut;
IF PRamRegDrivePDataIB THEN {
PDataI ← PRAMReg;
PParityI ← PRAMRegParity;
};
END;
END;
RegisterCells[];
END.