CachePInterfacePCAMDriver.rose
Last edited by: Barth, July 3, 1984 5:57:31 pm PDT
Last edited by: Curry, January 29, 1985 9:30:00 pm PST
Imports BitOps, BitSwOps;
Open BitOps, BitSwOps;
CELLTYPE "PCAMDriver"
PORTS[
Timing and housekeeping interface
Vdd, Gnd<BOOL,
CAM interface
CAMPage, nCAMPage=SWITCH[24]-(Special XPhobic),
CAMBlock, nCAMBlock=SWITCH[4]-(Special XPhobic),
Internal processor interface
PDataI<INT[32],
PCAMDriver interface
VARegSensePDataIA, LastRefRegSenseVARegB, PageDriveCAMBitsA, BlockDriveCAMBitsA<BOOL,
RefMatchesLastRefReg>BOOL
]
State
PageReg, LastRefPageReg: BitDWord,
BlockReg, LastRefBlockReg: BitWord
EvalSimple
IF VARegSensePDataIA THEN {
PageReg ← MDTD[PDataI, 32, 0, 24, PageReg, 24, 0, 24];
BlockReg ← MDTW[PDataI, 32, 24, 4, BlockReg, 4, 0, 4]
};
IF LastRefRegSenseVARegB THEN {
LastRefPageReg ← PageReg;
LastRefBlockReg ← BlockReg;
};
TRUSTED {
cpd: SwitchMWord ← DESCRIPTOR[CAMPage];
ncpd: SwitchMWord ← DESCRIPTOR[nCAMPage];
cbd: SwitchMWord ← DESCRIPTOR[CAMBlock];
ncbd: SwitchMWord ← DESCRIPTOR[nCAMBlock];
ps: SwitchTypes.Strength ← IF PageDriveCAMBitsA THEN driveStrong ELSE none;
bs: SwitchTypes.Strength ← IF BlockDriveCAMBitsA THEN driveStrong ELSE none;
SCDTS[PageReg, 24, 0, 24, cpd, 24, 0, 24, [[ps, L], [ps, H]]];
SCDTS[PageReg, 24, 0, 24, ncpd, 24, 0, 24, [[ps, H], [ps, L]]];
SCWTS[BlockReg, 4, 0, 4, cbd, 4, 0, 4, [[bs, L], [bs, H]]];
SCWTS[BlockReg, 4, 0, 4, ncbd, 4, 0, 4, [[bs, H], [bs, L]]];
};
RefMatchesLastRefReg ← PageReg=LastRefPageReg AND BlockReg=LastRefBlockReg;
ENDCELLTYPE