
<<CachePCtl.rose>>
<<Last edited by: Barth, June 20, 1984 6:29:10 pm PDT>>

Imports BitOps, BitSwOps, Dragon;
Open BitOps, BitSwOps, Dragon;

PCtl: CELL[

<<Timing and housekeeping interface>>
Vdd, Gnd<BOOL,
LatchBias<BOOL,
<<>>
<<Buffered timing and housekeeping interface>>
PhAb, PhBb<BOOL,
PhAh, PhBh<BOOL,
Resetb<BOOL, 

<<Cell control>>
PStore, nPStore>BOOL, PQSel>INT[4],
SenseVMatch>BOOL,

<<P control <=> M control>>
MDoneAB, MHeldAB<BOOL,
MFaultAB<EnumType["Dragon.PBusFaults"],
PAdrHigh, PAdrLowToM>BOOL,
PCmdToMAB>EnumType["Dragon.PBusCommands"],

<<Debug interface>>
DoShiftBA, DoExecuteBA<BOOL,
<<>>
<<Internal processor interface>>
PDataI<INT[32],
DrivePData, DrivePDataI>BOOL,
PCmdI<EnumType["Dragon.PBusCommands"],
PRejectDriveHigh, PRejectDriveLow>BOOL,
PFaultDrive>BOOL,
PFaultI>EnumType["Dragon.PBusFaults"],
PNPErrorDriveLow>BOOL,
<<>>
<<More debug interface>>
ShiftFeedBack, nShiftFeedBack, ShiftEqual, nShiftEqual, ShiftShift, nShiftShift>BOOL,
ShiftDataToPCtl<BOOL,
ShiftDataToPRAMDriver>BOOL,
<<>>
<<PCAMDriver interface>>
PDataIToVAReg>BOOL,
ReadVAReg, nReadVAReg>BOOL,

<<PRAMDriver interface>>
nPBitsPrecharge, MuxRight, MuxLeft, PBitsDrive, nPBitsDrive, PRamRegToPDataI, nPRamRegToPDataI, SensePBits, SensePDataI, 
ParityIn>BOOL,
ParityOut<BOOL,
ReadPRAMReg, nReadPRAMReg>BOOL
]

State
pCmdLatch: PBusCommands,
pShift, npShift: BitWord,
rejectA, rejectB, parityError, parityErrorLatch: BOOL,
isNoOp, suppressVirtualAccess: BOOL,
rejectShift, nrejectShift, parityShift, nparityShift, requestShift, nrequestShift: BOOL,
loadEnable, nloadEnable, loadMustBeOne, nloadMustBeOne, readVA, nreadVA: BOOL,
mask, mustBeOne: BitWord,
pAdrLowShift, npAdrLowShift, pAdrHighShift, npAdrHighShift: BOOL,
requestMatch: BOOL,
ioReference, cacheStoreReference, cacheReference, fetchReference, storeReference, holdReference: BOOL,
shiftExecute, nShiftExecute: BOOL
EvalSimple
    Assert[NOT MoreThanOneOf[DoShiftBA, DoExecuteBA]];
IF Resetb THEN {
pCmdLatch _ NoOp;
rejectA _ FALSE;
rejectB _ FALSE;
parityError _ FALSE;
parityErrorLatch _ FALSE;
mask _ 0;
};
PDataIToVAReg _ PhAh AND NOT rejectB;
IF PDataIToVAReg THEN {
adrBits: BitWord _ 0;
    adrBits _ IBIW[EBFD[PDataI, 32, 2], adrBits, 4, 0];
    adrBits _ IBIW[EBFD[PDataI, 32, 3], adrBits, 4, 1];
    adrBits _ IBIW[EBFD[PDataI, 32, 22], adrBits, 4, 2];
    adrBits _ IBIW[EBFD[PDataI, 32, 23], adrBits, 4, 3];
requestMatch _ WAND[mask, adrBits]=WAND[mask, mustBeOne];
pCmdLatch _ PCmdI;
PAdrHigh _ EBFD[PDataI, 32, 30];
PAdrLowToM _ EBFD[PDataI, 32, 31];
};

ioReference _ pCmdLatch=IOFetch OR pCmdLatch=IOStore OR pCmdLatch=IOFetchHold OR pCmdLatch=IOStoreHold;
cacheStoreReference _ pCmdLatch=Store OR pCmdLatch=StoreHold;
cacheReference _ pCmdLatch=Fetch OR pCmdLatch=FetchHold OR cacheStoreReference;
fetchReference _ pCmdLatch=Fetch OR pCmdLatch=FetchHold OR pCmdLatch=IOFetch OR pCmdLatch=IOFetchHold;
holdReference _ pCmdLatch=FetchHold OR pCmdLatch=StoreHold OR pCmdLatch=IOFetchHold OR pCmdLatch=IOStoreHold;
storeReference _ cacheStoreReference OR pCmdLatch=IOStore OR pCmdLatch=IOStoreHold;

IF PhBh THEN rejectB _ NOT MDoneAB AND requestMatch AND (ioReference OR (holdReference AND NOT MHeldAB) OR (cacheReference AND 
(nVirtualMatch OR NOT nMatchTIP)) OR (cacheStoreReference AND (NOT nMatchPageClean OR NOT nMatchCellShared)));
IF PhAb THEN nMatchTIP _ TRUE;
IF PhAh THEN rejectA _ rejectB;
IF PhBh THEN isNoOp _ pCmdLatch=NoOp;
PStore _ cacheStoreReference;
suppressVirtualAccess _ (pCmdLatch=StoreHold AND NOT MHeldAB) OR (NOT cacheReference);
PAdrLow _ NOT suppressVirtualAccess AND PAdrLowToM;
nPAdrLow _ NOT suppressVirtualAccess AND NOT PAdrLowToM;
PCmdToMAB _ IF requestMatch THEN pCmdLatch ELSE NoOp;

PRejectDriveHigh _  PhBb AND requestMatch AND (rejectB OR (MDoneAB AND MFaultAB#None));
PRejectDriveLow _ PhAb;
PFaultDrive _ (PhBb AND requestMatch) OR PhAb;
PFaultI _ IF MDoneAB AND PhBb THEN MFaultAB ELSE None;

ParityIn _ FALSE;
IF PhAh THEN parityError _ ParityOut AND NOT rejectB AND NOT isNoOp;
IF PhBh AND parityError THEN parityErrorLatch _ TRUE;
PNPErrorDriveLow _ parityErrorLatch;

DrivePData _ PhBh AND requestMatch AND fetchReference;
DrivePDataI _ NOT DrivePData;

nPBitsPrecharge _ NOT PhAb;
MuxLeft _ NOT PAdrHigh OR ioReference;
MuxRight _ NOT MuxLeft;
PBitsDrive _ PhBh AND storeReference;
nPBitsDrive _ NOT PBitsDrive;
PRamRegToPDataI _ PhBh AND fetchReference;
nPRamRegToPDataI _ NOT PRamRegToPDataI;
SensePBits _ PRamRegToPDataI;
SensePDataI _ PhBh AND storeReference AND NOT rejectA;

ShiftEqual _ PhBb;
nShiftEqual _ NOT ShiftEqual;
ShiftFeedBack _ PhAb AND NOT (DoShiftBA OR DoExecuteBA);
nShiftFeedBack _ NOT ShiftFeedBack;
ShiftShift _ PhAb AND DoShiftBA;
nShiftShift _ NOT ShiftShift;
shiftExecute _ PhAb AND DoExecuteBA;
nShiftExecute _ NOT shiftExecute;

ShiftToEnable _ (shiftExecute AND loadEnable) OR Resetb;
ShiftToMustBeOne _ (shiftExecute AND loadMustBeOne) OR Resetb;
ReadVAReg _ shiftExecute AND readVA;
nReadVAReg _ NOT ReadVAReg;
ReadPRAMReg _ shiftExecute;
nReadPRAMReg _ nShiftExecute;
IF shiftExecute THEN {
IF readVA THEN npShift _ WNOT[LOOPHOLE[pCmdLatch], 4];
IF loadEnable THEN mask _ pShift;
IF loadMustBeOne THEN mustBeOne _ pShift;
nrejectShift _ rejectB;
nparityShift _ parityErrorLatch;
nrequestShift _ requestMatch;
npAdrLowShift _ PAdrLowToM;
npAdrHighShift _ PAdrHigh;
};

IF ShiftShift THEN {
nloadEnable _ NOT ShiftDataToPCtl;
nloadMustBeOne _ NOT loadEnable;
npShift _ MWTW[WNOT[pShift, 4], 4, 0, 3, npShift, 4, 1, 3];
npShift _ IBIW[NOT loadMustBeOne, npShift, 4, 0];
nrejectShift _ NOT EBFW[pShift, 4, 3];
nparityShift _ NOT rejectShift;
nrequestShift _ NOT parityShift;
nreadVA _ NOT requestShift;
npAdrLowShift _ NOT readVA;
npAdrHighShift _ NOT pAdrLowShift;
};
IF ShiftFeedBack THEN {
nloadEnable _ NOT loadEnable;
nloadMustBeOne _ NOT loadMustBeOne;
npShift _ MWTW[WNOT[pShift, 4], 4, 0, 4, npShift, 4, 0, 4];
nrejectShift _ NOT rejectShift;
nparityShift _ NOT parityShift;
nrequestShift _ NOT requestShift;
nreadVA _ NOT readVA;
npAdrLowShift _ NOT pAdrLowShift;
npAdrHighShift _ NOT pAdrHighShift;
};
IF ShiftEqual THEN {
loadEnable _ NOT nloadEnable;
loadMustBeOne _ NOT nloadMustBeOne;
pShift _ MWTW[WNOT[npShift, 4], 4, 0, 4, pShift, 4, 0, 4];
rejectShift _ NOT nrejectShift;
parityShift _ NOT nparityShift;
requestShift _ NOT nrequestShift;
readVA _ NOT nreadVA;
pAdrLowShift _ NOT npAdrLowShift;
pAdrHighShift _ NOT npAdrHighShift;
};
ShiftDataToPRAMDriver _ pAdrHighShift;
ENDCELL