CachePCtl.rose
Last edited by: Barth, June 20, 1984 6:29:10 pm PDT
Imports BitOps, BitSwOps, Dragon;
Open BitOps, BitSwOps, Dragon;
PCtl: CELL[
Timing and housekeeping interface
Vdd, Gnd<BOOL,
LatchBias<BOOL,
Buffered timing and housekeeping interface
PhAb, PhBb<BOOL,
PhAh, PhBh<BOOL,
Resetb<BOOL,
Cell control
PStore, nPStore>BOOL, PQSel>INT[4],
SenseVMatch>BOOL,
P control <=> M control
MDoneAB, MHeldAB<BOOL,
MFaultAB<EnumType["Dragon.PBusFaults"],
PAdrHigh, PAdrLowToM>BOOL,
PCmdToMAB>EnumType["Dragon.PBusCommands"],
Debug interface
DoShiftBA, DoExecuteBA<BOOL,
Internal processor interface
PDataI<INT[32],
DrivePData, DrivePDataI>BOOL,
PCmdI<EnumType["Dragon.PBusCommands"],
PRejectDriveHigh, PRejectDriveLow>BOOL,
PFaultDrive>BOOL,
PFaultI>EnumType["Dragon.PBusFaults"],
PNPErrorDriveLow>BOOL,
More debug interface
ShiftFeedBack, nShiftFeedBack, ShiftEqual, nShiftEqual, ShiftShift, nShiftShift>BOOL,
ShiftDataToPCtl<BOOL,
ShiftDataToPRAMDriver>BOOL,
PCAMDriver interface
PDataIToVAReg>BOOL,
ReadVAReg, nReadVAReg>BOOL,
PRAMDriver interface
nPBitsPrecharge, MuxRight, MuxLeft, PBitsDrive, nPBitsDrive, PRamRegToPDataI, nPRamRegToPDataI, SensePBits, SensePDataI, ParityIn>BOOL,
ParityOut<BOOL,
ReadPRAMReg, nReadPRAMReg>BOOL
]
State
pCmdLatch: PBusCommands,
pShift, npShift: BitWord,
rejectA, rejectB, parityError, parityErrorLatch: BOOL,
isNoOp, suppressVirtualAccess: BOOL,
rejectShift, nrejectShift, parityShift, nparityShift, requestShift, nrequestShift: BOOL,
loadEnable, nloadEnable, loadMustBeOne, nloadMustBeOne, readVA, nreadVA: BOOL,
mask, mustBeOne: BitWord,
pAdrLowShift, npAdrLowShift, pAdrHighShift, npAdrHighShift: BOOL,
requestMatch: BOOL,
ioReference, cacheStoreReference, cacheReference, fetchReference, storeReference, holdReference: BOOL,
shiftExecute, nShiftExecute: BOOL
EvalSimple
Assert[NOT MoreThanOneOf[DoShiftBA, DoExecuteBA]];
IF Resetb THEN {
pCmdLatch ← NoOp;
rejectA ← FALSE;
rejectB ← FALSE;
parityError ← FALSE;
parityErrorLatch ← FALSE;
mask ← 0;
};
PDataIToVARegPhAh AND NOT rejectB;
IF PDataIToVAReg THEN {
adrBits: BitWord ← 0;
adrBits ← IBIW[EBFD[PDataI, 32, 2], adrBits, 4, 0];
adrBits ← IBIW[EBFD[PDataI, 32, 3], adrBits, 4, 1];
adrBits ← IBIW[EBFD[PDataI, 32, 22], adrBits, 4, 2];
adrBits ← IBIW[EBFD[PDataI, 32, 23], adrBits, 4, 3];
requestMatch ← WAND[mask, adrBits]=WAND[mask, mustBeOne];
pCmdLatch ← PCmdI;
PAdrHigh ← EBFD[PDataI, 32, 30];
PAdrLowToM ← EBFD[PDataI, 32, 31];
};
ioReference ← pCmdLatch=IOFetch OR pCmdLatch=IOStore OR pCmdLatch=IOFetchHold OR pCmdLatch=IOStoreHold;
cacheStoreReference ← pCmdLatch=Store OR pCmdLatch=StoreHold;
cacheReference ← pCmdLatch=Fetch OR pCmdLatch=FetchHold OR cacheStoreReference;
fetchReference ← pCmdLatch=Fetch OR pCmdLatch=FetchHold OR pCmdLatch=IOFetch OR pCmdLatch=IOFetchHold;
holdReference ← pCmdLatch=FetchHold OR pCmdLatch=StoreHold OR pCmdLatch=IOFetchHold OR pCmdLatch=IOStoreHold;
storeReference ← cacheStoreReference OR pCmdLatch=IOStore OR pCmdLatch=IOStoreHold;
IF PhBh THEN rejectB ← NOT MDoneAB AND requestMatch AND (ioReference OR (holdReference AND NOT MHeldAB) OR (cacheReference AND (nVirtualMatch OR NOT nMatchTIP)) OR (cacheStoreReference AND (NOT nMatchPageClean OR NOT nMatchCellShared)));
IF PhAb THEN nMatchTIP ← TRUE;
IF PhAh THEN rejectA ← rejectB;
IF PhBh THEN isNoOp ← pCmdLatch=NoOp;
PStore ← cacheStoreReference;
suppressVirtualAccess ← (pCmdLatch=StoreHold AND NOT MHeldAB) OR (NOT cacheReference);
PAdrLow ← NOT suppressVirtualAccess AND PAdrLowToM;
nPAdrLow ← NOT suppressVirtualAccess AND NOT PAdrLowToM;
PCmdToMAB ← IF requestMatch THEN pCmdLatch ELSE NoOp;
PRejectDriveHigh ← PhBb AND requestMatch AND (rejectB OR (MDoneAB AND MFaultAB#None));
PRejectDriveLow ← PhAb;
PFaultDrive ← (PhBb AND requestMatch) OR PhAb;
PFaultI ← IF MDoneAB AND PhBb THEN MFaultAB ELSE None;
ParityIn ← FALSE;
IF PhAh THEN parityError ← ParityOut AND NOT rejectB AND NOT isNoOp;
IF PhBh AND parityError THEN parityErrorLatch ← TRUE;
PNPErrorDriveLow ← parityErrorLatch;
DrivePData ← PhBh AND requestMatch AND fetchReference;
DrivePDataI ← NOT DrivePData;
nPBitsPrecharge ← NOT PhAb;
MuxLeft ← NOT PAdrHigh OR ioReference;
MuxRight ← NOT MuxLeft;
PBitsDrive ← PhBh AND storeReference;
nPBitsDrive ← NOT PBitsDrive;
PRamRegToPDataI ← PhBh AND fetchReference;
nPRamRegToPDataI ← NOT PRamRegToPDataI;
SensePBits ← PRamRegToPDataI;
SensePDataI ← PhBh AND storeReference AND NOT rejectA;
ShiftEqual ← PhBb;
nShiftEqual ← NOT ShiftEqual;
ShiftFeedBack ← PhAb AND NOT (DoShiftBA OR DoExecuteBA);
nShiftFeedBack ← NOT ShiftFeedBack;
ShiftShift ← PhAb AND DoShiftBA;
nShiftShift ← NOT ShiftShift;
shiftExecute ← PhAb AND DoExecuteBA;
nShiftExecute ← NOT shiftExecute;
ShiftToEnable ← (shiftExecute AND loadEnable) OR Resetb;
ShiftToMustBeOne ← (shiftExecute AND loadMustBeOne) OR Resetb;
ReadVAReg ← shiftExecute AND readVA;
nReadVAReg ← NOT ReadVAReg;
ReadPRAMReg ← shiftExecute;
nReadPRAMReg ← nShiftExecute;
IF shiftExecute THEN {
IF readVA THEN npShift ← WNOT[LOOPHOLE[pCmdLatch], 4];
IF loadEnable THEN mask ← pShift;
IF loadMustBeOne THEN mustBeOne ← pShift;
nrejectShift ← rejectB;
nparityShift ← parityErrorLatch;
nrequestShift ← requestMatch;
npAdrLowShift ← PAdrLowToM;
npAdrHighShift ← PAdrHigh;
};
IF ShiftShift THEN {
nloadEnable ← NOT ShiftDataToPCtl;
nloadMustBeOne ← NOT loadEnable;
npShift ← MWTW[WNOT[pShift, 4], 4, 0, 3, npShift, 4, 1, 3];
npShift ← IBIW[NOT loadMustBeOne, npShift, 4, 0];
nrejectShift ← NOT EBFW[pShift, 4, 3];
nparityShift ← NOT rejectShift;
nrequestShift ← NOT parityShift;
nreadVA ← NOT requestShift;
npAdrLowShift ← NOT readVA;
npAdrHighShift ← NOT pAdrLowShift;
};
IF ShiftFeedBack THEN {
nloadEnable ← NOT loadEnable;
nloadMustBeOne ← NOT loadMustBeOne;
npShift ← MWTW[WNOT[pShift, 4], 4, 0, 4, npShift, 4, 0, 4];
nrejectShift ← NOT rejectShift;
nparityShift ← NOT parityShift;
nrequestShift ← NOT requestShift;
nreadVA ← NOT readVA;
npAdrLowShift ← NOT pAdrLowShift;
npAdrHighShift ← NOT pAdrHighShift;
};
IF ShiftEqual THEN {
loadEnable ← NOT nloadEnable;
loadMustBeOne ← NOT nloadMustBeOne;
pShift ← MWTW[WNOT[npShift, 4], 4, 0, 4, pShift, 4, 0, 4];
rejectShift ← NOT nrejectShift;
parityShift ← NOT nparityShift;
requestShift ← NOT nrequestShift;
readVA ← NOT nreadVA;
pAdrLowShift ← NOT npAdrLowShift;
pAdrHighShift ← NOT npAdrHighShift;
};
ShiftDataToPRAMDriver ← pAdrHighShift;
ENDCELL