CachePCAMDriver.rose
Last edited by: Barth, May 31, 1984 5:38:34 pm PDT
Imports BitOps, BitSwOps, Dragon;
Open BitOps, BitSwOps, Dragon;
PCAMDriver: CELL[
Timing and housekeeping interface
Vdd, Gnd<BOOL,
LatchBias<BOOL,
CAM interface
VirtualPage, nVirtualPage>INT[24],
VirtualBlock, nVirtualBlock>INT[6],
Debug interface
ShiftDataToPCAM<BOOL,
Internal processor interface
PDataI<INT[32],
More debug interface
ShiftFeedBack, nShiftFeedBack, ShiftEqual, nShiftEqual, ShiftShift, nShiftShift<BOOL,
ShiftDataToPCtl>BOOL,
PCAMDriver interface
PDataIToVAReg<BOOL,
ReadVAReg, nReadVAReg<BOOL
]
State
shiftData, nshiftData: BitDWord,
pageAddress: BitDWord,
blockAddress: BitWord
EvalSimple
Assert[NOT MoreThanOneOf[ShiftFeedBack, nShiftFeedBack]];
Assert[NOT MoreThanOneOf[ShiftEqual, nShiftEqual]];
Assert[NOT MoreThanOneOf[ShiftShift, nShiftShift]];
Assert[NOT MoreThanOneOf[ReadVAReg, nReadVAReg]];
Assert[NOT MoreThanOneOf[ShiftFeedBack, ShiftShift, ShiftEqual, ReadVAReg]];
IF ShiftShift THEN {
nshiftData ← MDTD[DNOT[shiftData, 30], 30, 0, 29, nshiftData, 30, 1, 29];
nshiftData ← IBID[NOT ShiftDataToPCAM, nshiftData, 30, 0];
};
IF ShiftFeedBack THEN {
nshiftData ← MDTD[DNOT[shiftData, 30], 30, 0, 30, nshiftData, 30, 0, 30];
};
IF ShiftEqual THEN {
shiftData ← MDTD[DNOT[nshiftData, 30], 30, 0, 30, shiftData, 30, 0, 30];
ShiftDataToPCtl ← EBFD[shiftData, 30, 29];
};
IF PDataIToVAReg THEN {
pageAddress ← MDTD[PDataI, 32, 0, 24, pageAddress, 24, 0, 24];
blockAddress ← MDTW[PDataI, 32, 24, 6, blockAddress, 6, 0, 6]
};
VirtualPage ← pageAddress;
nVirtualPage ← DNOT[VirtualPage, 24];
VirtualBlock ← blockAddress;
nVirtualBlock ← WNOT[VirtualBlock, 6];
IF ReadVAReg THEN {
nshiftData ← MDTD[DNOT[pageAddress, 24], 24, 0, 24, nshiftData, 30, 0, 24];
nshiftData ← MWTD[WNOT[blockAddress, 6], 6, 0, 6, nshiftData, 30, 24, 6];
};
ENDCELL