<> <<.. functions for Dragon Cache Rosemary simulations. For now it assumes that there is only virtual memory. Mapping and map operations are not yet implemented.>> <<>> <> <> DIRECTORY BitOps, BitSwOps, Dragon USING [Word], IO USING [STREAM], Rope USING [ROPE]; CacheOps: CEDAR DEFINITIONS = BEGIN PageSize: NAT = 256; StdLinesPerCache: NAT = 64; WordsPerLine: NAT = 4; PreFetchAdrCmd: TYPE = MACHINE DEPENDENT {VictimReal(0), RefRealMap(1), RefRealAssemble(2), RefVirtual(3)}; VirtualMemory: TYPE = REF; defaultVM, lastVM: VirtualMemory; NewVirtualMemory: PROC RETURNS [ m: VirtualMemory ]; VirtualMemoryFromFile: PROC [ m: VirtualMemory, fileName: Rope.ROPE ]; VirtualMemoryFromStream: PROC [ m: VirtualMemory, s: IO.STREAM ]; VMFileFormat: ERROR; NewVirtualMemoryFromFile: PROC [ fileName: Rope.ROPE ] RETURNS [ m: VirtualMemory ]; << = {m _ NewVirtualMemory[]; VirtualMemoryFromFile[m, fileName]};>> <<>> VirtualMemoryToStream: PROC [ m: VirtualMemory, s: IO.STREAM ]; EnumerateVirtualMemory: PROC [ m: VirtualMemory, wdProc: PROC [ addr, data: Dragon.Word, readOnly, dirty: BOOL _ FALSE, privateData: REF _ NIL ], privateData: REF _ NIL ]; Cache: TYPE = REF; lastCache: Cache; NewCache: PROC [ mem: REF ANY _ NIL, nLines: NAT _ StdLinesPerCache ] RETURNS [ c: Cache ]; AccessPurpose: TYPE = {read, write}; Access: PROC [ c: Cache, address: Dragon.Word, purpose: AccessPurpose _ read, cycleNow: INT _ 0 ] RETURNS [ data: Dragon.Word, rejectCycles: NAT, pageFault, writeProtect: BOOL ]; Write: PROC [ c: Cache, address, data: Dragon.Word ]; IORead: PROC [ c: Cache, address: Dragon.Word, cycleNow: INT _ 0 ] RETURNS [ data: Dragon.Word, rejectCycles: NAT ]; IOWrite: PROC [ c: Cache, address, data: Dragon.Word, cycleNow: INT _ 0 ] RETURNS [ rejectCycles: NAT ]; SetFlags: PROC [ c: Cache, address: Dragon.Word, writeProtect, dirty, mapped: BOOL ]; SetIntervalFlags: PROC [ c: Cache, startAddress, endAddress -- [startAddress..endAddress] -- : Dragon.Word, writeProtect, dirty, mapped: BOOL ]; GetFlags: PROC [ c: Cache, address: Dragon.Word ] RETURNS [ writeProtect, dirty, mapped: BOOL ]; Parity32: PROC [ w: Dragon.Word ] RETURNS [ odd: BOOL ]; Parity16: PROC [ n: CARDINAL ] RETURNS [ odd: BOOL ]; DriveBus: PROC [busd, nbusd: BitSwOps.SwitchMWord, drive: BOOL, offset: CARDINAL, RAMReg: BitOps.BitDWord, RAMRegParity: BOOL]; END.