CacheMicroCodeB.mesa
Last Edited by: Barth, July 27, 1984 5:05:09 pm PDT
DIRECTORY CacheMicroMachine;
CacheMicroCodeB: CEDAR PROGRAM
IMPORTS CacheMicroMachine =
BEGIN OPEN CacheMicroMachine;
The box which recodes MCmdIn can be made very simple if MBusCommands has 1 bit on for each of the commands interpreted by the slave, i.e. if ReadQuad, WriteQuad, WriteSingle, and ChangeFlags have one of the four bits on (or off, depending on whether the recoder inverts or not) and all other commands are classed by checking if more than one bit is on.
Slave;
Sequence[6]; -- DataTransport(0), IORead(5), IOReadDone(6), IOWrite(7), IOWriteDone(8), Reserve9(9), Reserve10(10), Reserve11(11), Reserve12(12), Reserve13(13), Reserve14(14), NoOp(15)
Cycle[1, LIST[$CAMRegSenseMDataI, $SenseRMatch, $SampleMAdr2831, $DriveSharedHigh, $Done, $SenseMDataI, $MDataIToFaults, $FlagLatch, $IfGrantThenGetAdrElseRefreshToDecoder, $SampleDirtyBits, $FormAddress]];
Sequence[1]; -- ReadQuad(1)
Cycle[1, LIST[$SampleRealMatch, $DriveSharedLow, $SetShared, $Adr2829ToMQSel, $SelectRealData, $MCmdDrive, $MCmdDriveToNoOp]];
Cycle[2, LIST[$SenseMBits, $DriveMDataI, $MDataDrive, $MCmdDrive, $MCmdDriveToDataTransport, $BCheckParity, $Adr2829ToMQSel, $SelectRealData, $IncrementMAdrCtr]];
Cycle[3, LIST[$SenseMBits, $DriveMDataI, $MDataDrive, $MCmdDrive, $MCmdDriveToDataTransport, $BCheckParity, $Adr2829ToMQSel, $SelectRealData, $IncrementMAdrCtr]];
Cycle[4, LIST[$SenseMBits, $DriveMDataI, $MDataDrive, $MCmdDrive, $MCmdDriveToDataTransport, $BCheckParity, $Adr2829ToMQSel, $SelectRealData, $IncrementMAdrCtr]];
Cycle[5, LIST[$SenseMBits, $DriveMDataI, $MDataDrive, $MCmdDrive, $MCmdDriveToDataTransport, $BCheckParity, $Done, $ForceIdle, $FetchAddress, $FormAddress, $SampleDirtyBits]];
Sequence[2]; -- WriteQuad(2)
Cycle[1, LIST[$SampleRealMatch, $DriveSharedLow, $MCmdDrive, $MCmdDriveToDataTransport, $SenseMDataI, $Adr2829ToMQSel, $SelectRealData, $DriveMBits, $ACheckParity]];
Cycle[2, LIST[$MCmdDrive, $MCmdDriveToDataTransport, $SenseMDataI, $Adr2829ToMQSel, $SelectRealData, $IncrementMAdrCtr, $DriveMBits, $ACheckParity]];
Cycle[3, LIST[$MCmdDrive, $MCmdDriveToDataTransport, $SenseMDataI, $Adr2829ToMQSel, $SelectRealData, $IncrementMAdrCtr, $DriveMBits, $ACheckParity]];
Cycle[4, LIST[$MCmdDrive, $MCmdDriveToDataTransport, $SenseMDataI, $Adr2829ToMQSel, $SelectRealData, $IncrementMAdrCtr, $DriveMBits, $ACheckParity, $Done, $ForceIdle, $FetchAddress, $FormAddress, $SampleDirtyBits]];
Sequence[3]; -- WriteSingle(3)
Cycle[1, LIST[$SampleRealMatch, $DriveSharedLow, $SenseMDataI, $Adr2829ToMQSel, $SelectRealData, $DriveMBits, $ResetMaster, $ACheckParity, $Done, $ForceIdle, $FetchAddress, $FormAddress, $SampleDirtyBits]];
Sequence[4]; -- ChangeFlags(4)
Cycle[1, LIST[$SelPageFlags, $SetRPDirtyVPValid, $Done, $ForceIdle]]; -- some unknown number of noops must take place after this one to allow the master sequencer to recomputer what needs to happen before the m bus grant can be changed, determine this number and make the map processor emit the appropriate number of noops before saying done to whatever invoked the operation.
END.