CacheMRAMDriver.rose
Last edited by: Barth, May 15, 1984 9:58:33 am PDT
Imports BitOps, BitSwOps, Dragon;
Open BitOps, BitSwOps, Dragon;
MRAMDriver: CELL[
Timing and housekeeping interface
Vdd, Gnd<BOOL,
LatchBias<BOOL,
RAM access
PBits, nPBits=SWITCH[66]-S-X,
MBits, nMBits=SWITCH[66]-S-X,
Internal main memory interface
MDataI=INT[32],
MParityI=BOOL,
More debug interface
ShiftDataToMRAM<BOOL,
ShiftDataToMCtl>BOOL,
ShiftFeedBack, nShiftFeedBack, ShiftEqual, nShiftEqual, ShiftShift, nShiftShift<BOOL,
MRAMDriver interface
nMBitsPrecharge, MuxRight, MuxLeft, MBitsDrive, nMBitsDrive, MRamRegToMDataI, nMRamRegToMDataI, SenseMBits, SenseMDataI, ParityIn<BOOL,
ParityOut>BOOL,
SensePBitsLeft, SensePBitsRight, DrivePBits, nDrivePBits<BOOL,
MRamRegToMBits, nMRamRegToMBits<BOOL,
ShiftToMBits, nShiftToMBits, MBitsToShift, nMBitsToShift<BOOL
]
State
mRAMReg, shiftData, nShiftData: BitDWord,
mRAMRegParity, shiftDataParity, nShiftDataParity: BOOL
EvalSimple
Assert[NOT MoreThanOneOf[NOT nMBitsPrecharge, MBitsDrive]];
Assert[(NOT MBitsDrive) OR (MRamRegToMBits OR ShiftToMBits)];
Assert[MuxRight OR MuxLeft];
Assert[NOT MoreThanOneOf[MuxRight, MuxLeft]];
Assert[NOT MoreThanOneOf[MBitsDrive, nMBitsDrive]];
Assert[NOT MoreThanOneOf[MBitsToShift, nMBitsToShift]];
Assert[NOT MoreThanOneOf[ShiftToMBits, nShiftToMBits]];
Assert[NOT MoreThanOneOf[MRamRegToMDataI, nMRamRegToMDataI]];
Assert[NOT MoreThanOneOf[DrivePBits, nDrivePBits]];
Assert[NOT MoreThanOneOf[ShiftFeedBack, nShiftFeedBack]];
Assert[NOT MoreThanOneOf[ShiftEqual, nShiftEqual]];
Assert[NOT MoreThanOneOf[ShiftShift, nShiftShift]];
Assert[NOT MoreThanOneOf[ShiftShift, ShiftFeedBack, ShiftEqual]];
Assert[NOT MoreThanOneOf[SenseMBits, MBitsDrive]];
TRUSTED {
mbitd: SwitchMWord ← DESCRIPTOR[MBits];
nmbitd: SwitchMWord ← DESCRIPTOR[nMBits];
s: SwitchTypes.Strength ← IF MBitsDrive THEN driveStrong ELSE none;
mBitData: BitDWord;
mBitParity: BOOL;
offset: CARDINAL ← IF MuxLeft THEN 0 ELSE 1;
IF SenseMDataI THEN {
mRAMReg ← MDataI;
mRAMRegParity ← MParityI;
};
IF MRamRegToMBits THEN {
mBitData ← mRAMReg;
mBitParity ← mRAMRegParity;
}
ELSE { -- assume that ShiftToMBits is asserted
mBitData ← shiftData;
mBitParity ← shiftDataParity;
};
FOR i:CARDINAL IN [0..32) DO
SIBIS[EBFD[mBitData, 32, i], mbitd, 66, (2*i)+offset, [[s, L], [s, H]]];
SIBIS[EBFD[mBitData, 32, i], nmbitd, 66, (2*i)+offset, [[s, H], [s, L]]];
SIBIS[FALSE, mbitd, 66, (2*i)+1-offset, [[none, X], [none, X]]];
SIBIS[FALSE, nmbitd, 66, (2*i)+1-offset, [[none, X], [none, X]]];
ENDLOOP;
SIBIS[mBitParity, mbitd, 66, 64+offset, [[s, L], [s, H]]];
SIBIS[mBitParity, nmbitd, 66, 64+offset, [[s, H], [s, L]]];
SIBIS[FALSE, mbitd, 66, 65-offset, [[none, X], [none, X]]];
SIBIS[FALSE, nmbitd, 66, 65-offset, [[none, X], [none, X]]];
IF NOT nMBitsPrecharge THEN {
SCDTS[BitDWordOnes, 32, 0, 32, mbitd, 66, 0, 32, [[none, X], [drive, H]]];
SCDTS[BitDWordOnes, 32, 0, 32, nmbitd, 66, 0, 32, [[none, X], [drive, H]]];
SCDTS[BitDWordOnes, 32, 0, 32, mbitd, 66, 32, 32, [[none, X], [drive, H]]];
SCDTS[BitDWordOnes, 32, 0, 32, nmbitd, 66, 32, 32, [[none, X], [drive, H]]];
SCWTS[BitWordOnes, 16, 0, 2, mbitd, 66, 64, 2, [[none, X], [drive, H]]];
SCWTS[BitWordOnes, 16, 0, 2, nmbitd, 66, 64, 2, [[none, X], [drive, H]]];
};
FOR i:CARDINAL IN [0..32) DO
mBitData ← IBID[EBFS[mbitd, 66, (2*i)+offset], mBitData, 32, i];
ENDLOOP;
mBitParity ← EBFS[mbitd, 66, 64+offset];
IF SenseMBits THEN {
mRAMReg ← mBitData;
mRAMRegParity ← mBitParity;
};
IF MBitsToShift THEN {
nShiftData ← DNOT[mBitData, 32];
nShiftDataParity ← NOT mBitParity;
};
};
IF MRamRegToMDataI THEN {
MDataI ← mRAMReg;
MParityI ← mRAMRegParity;
};
TRUSTED {
pbitd: SwitchMWord ← DESCRIPTOR[PBits];
npbitd: SwitchMWord ← DESCRIPTOR[nPBits];
s: SwitchTypes.Strength ← IF DrivePBits THEN driveStrong ELSE none;
FOR i:CARDINAL IN [0..32) DO
SIBIS[EBFD[mRAMReg, 32, i], pbitd, 66, (2*i), [[s, L], [s, H]]];
SIBIS[EBFD[mRAMReg, 32, i], npbitd, 66, (2*i), [[s, H], [s, L]]];
SIBIS[FALSE, pbitd, 66, (2*i)+1, [[none, X], [none, X]]];
SIBIS[FALSE, npbitd, 66, (2*i)+1, [[none, X], [none, X]]];
ENDLOOP;
SIBIS[mRAMRegParity, pbitd, 66, 64, [[s, L], [s, H]]];
SIBIS[mRAMRegParity, npbitd, 66, 64, [[s, H], [s, L]]];
SIBIS[FALSE, pbitd, 66, 65, [[none, X], [none, X]]];
SIBIS[FALSE, npbitd, 66, 65, [[none, X], [none, X]]];
IF SensePBitsLeft THEN {
pBitData: BitDWord;
FOR i:CARDINAL IN [0..32) DO
pBitData ← IBID[EBFS[pbitd, 66, 2*i], pBitData, 32, i];
ENDLOOP;
mRAMReg ← pBitData;
mRAMRegParity ← EBFS[pbitd, 66, 64];
};
IF SensePBitsRight THEN {
pBitData: BitDWord;
FOR i:CARDINAL IN [0..32) DO
pBitData ← IBID[EBFS[pbitd, 66, (2*i)+1], pBitData, 32, i];
ENDLOOP;
mRAMReg ← pBitData;
mRAMRegParity ← EBFS[pbitd, 66, 65];
};
};
IF ShiftFeedBack THEN {
nShiftData ← DNOT[shiftData, 32];
nShiftDataParity ← NOT shiftDataParity
};
IF ShiftShift THEN {
nShiftData ← MDTD[DNOT[shiftData, 32], 32, 1, 31, nShiftData, 32, 0, 31];
nShiftData ← IBID[NOT shiftDataParity, nShiftData, 32, 31];
nShiftDataParity ← NOT ShiftDataToMRAM
};
IF ShiftEqual THEN {
shiftDataParity ← NOT nShiftDataParity;
shiftData ← DNOT[nShiftData, 32];
ShiftDataToMCtl ← EBFD[shiftData, 32, 0];
};
ParityOut ← ParityIn;
FOR j:CARDINAL IN [0..32) DO
IF EBFD[mRAMReg, 32, j] THEN ParityOut ← NOT ParityOut;
ENDLOOP;
IF mRAMRegParity THEN ParityOut ← NOT ParityOut;
ENDCELL