
    <<CacheMInterfaceMSequencer.Mesa>>
    <<created by RoseTranslate from CacheMInterfaceMSequencer.Rose of January 29, 1985 9:37:09 pm PST for curry.pa at January 29, 1985 
    9:37:58 pm PST>>


    DIRECTORY
        RoseTypes, RoseCreate, BitOps, Dragon, CacheOps;

    CacheMInterfaceMSequencer: CEDAR PROGRAM
        IMPORTS RoseCreate, BitOps, Dragon =

    BEGIN OPEN
        RoseTypes, BitOps, Dragon;

    <<Signal Type decls>>
        PBusFaults: TYPE = Dragon.PBusFaults;
        PBusCommands: TYPE = Dragon.PBusCommands;
        MBusCommands: TYPE = Dragon.MBusCommands;
        PreFetchAdrCmd: TYPE = CacheOps.PreFetchAdrCmd;


    RegisterCells: PROC =
        BEGIN
        [] _ RoseCreate.RegisterCellType[name: "MSequencer",
            expandProc: NIL,
            ioCreator: CreateMSequencerIO, initializer: InitializeMSequencer,
            evals: [EvalSimple: MSequencerEvalSimple],
            blackBox: NIL, stateToo: NIL,
            ports: CreateMSequencerPorts[],
            drivePrototype: NEW [MSequencerDrive]];
        END;
    otherss: SymbolTable _ RoseCreate.GetOtherss["CacheMInterfaceMSequencer.pass"];

    CreateMSequencerPorts: PROC RETURNS [ports: Ports] = {ports _ 
    RoseCreate.PortsFromFile["CacheMInterfaceMSequencer.MSequencer.rosePorts"]};

    MSequencerIORef: TYPE = REF MSequencerIORec;
    MSequencerIORec: TYPE = MACHINE DEPENDENT RECORD [
        fill0(0:0..14): [0..32767],
        Vdd(0:15..15): BOOLEAN,
        fill1(1:0..14): [0..32767],
        Gnd(1:15..15): BOOLEAN,
        fill2(2:0..14): [0..32767],
        PhAb(2:15..15): BOOLEAN,
        fill3(3:0..14): [0..32767],
        PhBb(3:15..15): BOOLEAN,
        fill4(4:0..14): [0..32767],
        Resetb(4:15..15): BOOLEAN,
        fill5(5:0..14): [0..32767],
        nVQMatchB(5:15..15): BOOLEAN,
        fill6(6:0..14): [0..32767],
        nQuadSharedB(6:15..15): BOOLEAN,
        fill7(7:0..14): [0..32767],
        nRQMatchA(7:15..15): BOOLEAN,
        fill8(8:0..14): [0..32767],
        nPageDirtyB(8:15..15): BOOLEAN,
        fill9(9:0..14): [0..32767],
        nMapValidB(9:15..15): BOOLEAN,
        fill10(10:0..14): [0..32767],
        nRealBlockMatchA(10:15..15): BOOLEAN,
        fill11(11:0..14): [0..32767],
        nVirtualBlockMatchB(11:15..15): BOOLEAN,
        fill12(12:0..14): [0..32767],
        MDoneAB(12:15..15): BOOLEAN,
        fill13(13:0..14): [0..32767],
        MHeldAB(13:15..15): BOOLEAN,
        fill14(14:0..11): [0..4095],
        MFaultAB(14:12..15): PBusFaults,
        fill15(15:0..11): [0..4095],
        PCmdToMAB(15:12..15): PBusCommands,
        fill16(16:0..11): [0..4095],
        MCmdIn(16:12..15): MBusCommands,
        fill17(17:0..11): [0..4095],
        MCmdOutAB(17:12..15): MBusCommands,
        fill18(18:0..14): [0..32767],
        MCmdDriveC(18:15..15): BOOLEAN,
        MDataI(19:0..31): ARRAY [0..2) OF CARDINAL,
        fill20(21:0..14): [0..32767],
        MParityI(21:15..15): BOOLEAN,
        fill21(22:0..14): [0..32767],
        MDataDriveC(22:15..15): BOOLEAN,
        fill22(23:0..14): [0..32767],
        MSharedSense(23:15..15): BOOLEAN,
        fill23(24:0..14): [0..32767],
        MNSharedDriveHighC(24:15..15): BOOLEAN,
        fill24(25:0..14): [0..32767],
        MNSharedDriveLowC(25:15..15): BOOLEAN,
        fill25(26:0..14): [0..32767],
        MNErrorDriveLow(26:15..15): BOOLEAN,
        fill26(27:0..14): [0..32767],
        MRqIBA(27:15..15): BOOLEAN,
        fill27(28:0..14): [0..32767],
        MNewRqIBA(28:15..15): BOOLEAN,
        fill28(29:0..14): [0..32767],
        MNewRqEnableC(29:15..15): BOOLEAN,
        fill29(30:0..14): [0..32767],
        MGntSenseA(30:15..15): BOOLEAN,
        fill30(31:0..14): [0..32767],
        SuppressPSampleAB(31:15..15): BOOLEAN,
        fill31(32:0..14): [0..32767],
        MIsDoneAB(32:15..15): BOOLEAN,
        fill32(33:0..14): [0..32767],
        SetWantWSA(33:15..15): BOOLEAN,
        fill33(34:0..14): [0..32767],
        CheckFaultsAB(34:15..15): BOOLEAN,
        fill34(35:0..14): [0..32767],
        SenseSharedB(35:15..15): BOOLEAN,
        fill35(36:0..14): [0..32767],
        ReleaseMBusBA(36:15..15): BOOLEAN,
        fill36(37:0..14): [0..32767],
        ForceIdleAB(37:15..15): BOOLEAN,
        fill37(38:0..14): [0..32767],
        DoneAB(38:15..15): BOOLEAN,
        fill38(39:0..14): [0..32767],
        ForceSlaveBA(39:15..15): BOOLEAN,
        fill39(40:0..14): [0..32767],
        SenseReadyBA(40:15..15): BOOLEAN,
        fill40(41:0..14): [0..32767],
        MDataIToFaultsB(41:15..15): BOOLEAN,
        fill41(42:0..14): [0..32767],
        MapBitsToMDataIA(42:15..15): BOOLEAN,
        fill42(43:0..14): [0..32767],
        ACheckParityA(43:15..15): BOOLEAN,
        fill43(44:0..14): [0..32767],
        BCheckParityB(44:15..15): BOOLEAN,
        fill44(45:0..14): [0..32767],
        SampleRealMatchA(45:15..15): BOOLEAN,
        fill45(46:0..14): [0..32767],
        MCmdDriveA(46:15..15): BOOLEAN,
        fill46(47:0..14): [0..32767],
        MDataDriveA(47:15..15): BOOLEAN,
        fill47(48:0..14): [0..32767],
        DriveSharedHighA(48:15..15): BOOLEAN,
        fill48(49:0..14): [0..32767],
        DriveSharedLowA(49:15..15): BOOLEAN,
        fill49(50:0..14): [0..32767],
        MasterEnableMBusDriveAB(50:15..15): BOOLEAN,
        fill50(51:0..14): [0..32767],
        MCmdDriveToDataTransportAB(51:15..15): BOOLEAN,
        fill51(52:0..14): [0..32767],
        MCmdDriveToNoOpAB(52:15..15): BOOLEAN,
        fill52(53:0..13): [0..16383],
        GetAdrCmdBA(53:14..15): PreFetchAdrCmd,
        fill53(54:0..14): [0..32767],
        IsCleanBA(54:15..15): BOOLEAN,
        fill54(55:0..14): [0..32767],
        LatchSharedBA(55:15..15): BOOLEAN,
        fill55(56:0..14): [0..32767],
        MasterBA(56:15..15): BOOLEAN,
        fill56(57:0..14): [0..32767],
        MatchRealQuadAB(57:15..15): BOOLEAN,
        fill57(58:0..14): [0..32767],
        MatchRealBlockAB(58:15..15): BOOLEAN,
        fill58(59:0..14): [0..32767],
        ContinueBA(59:15..15): BOOLEAN,
        fill59(60:0..14): [0..32767],
        OneDirtyBA(60:15..15): BOOLEAN,
        fill60(61:0..14): [0..32767],
        SomeDirtyBA(61:15..15): BOOLEAN,
        fill61(62:0..14): [0..32767],
        MDataDriveDelayedA(62:15..15): BOOLEAN,
        fill62(63:0..8): [0..511],
        ROMSequenceBA(63:9..15): [0..127],
        fill63(64:0..14): [0..32767],
        ROMSlaveBA(64:15..15): BOOLEAN,
        fill64(65:0..8): [0..511],
        ROMCycleBA(65:9..15): [0..127],
        fill65(66:0..14): [0..32767],
        MRamRegParityOut(66:15..15): BOOLEAN];

    <<port indices:>>


    MSequencerDrive: TYPE = MACHINE DEPENDENT RECORD [
        fill0(0:0..14): [0 .. 32768),
        Vdd(0:15..15): BOOLEAN,
        fill1(1:0..14): [0 .. 32768),
        Gnd(1:15..15): BOOLEAN,
        fill2(2:0..14): [0 .. 32768),
        PhAb(2:15..15): BOOLEAN,
        fill3(3:0..14): [0 .. 32768),
        PhBb(3:15..15): BOOLEAN,
        fill4(4:0..14): [0 .. 32768),
        Resetb(4:15..15): BOOLEAN,
        fill5(5:0..14): [0 .. 32768),
        nVQMatchB(5:15..15): BOOLEAN,
        fill6(6:0..14): [0 .. 32768),
        nQuadSharedB(6:15..15): BOOLEAN,
        fill7(7:0..14): [0 .. 32768),
        nRQMatchA(7:15..15): BOOLEAN,
        fill8(8:0..14): [0 .. 32768),
        nPageDirtyB(8:15..15): BOOLEAN,
        fill9(9:0..14): [0 .. 32768),
        nMapValidB(9:15..15): BOOLEAN,
        fill10(10:0..14): [0 .. 32768),
        nRealBlockMatchA(10:15..15): BOOLEAN,
        fill11(11:0..14): [0 .. 32768),
        nVirtualBlockMatchB(11:15..15): BOOLEAN,
        fill12(12:0..14): [0 .. 32768),
        MDoneAB(12:15..15): BOOLEAN,
        fill13(13:0..14): [0 .. 32768),
        MHeldAB(13:15..15): BOOLEAN,
        fill14(14:0..14): [0 .. 32768),
        MFaultAB(14:15..15): BOOLEAN,
        fill15(15:0..14): [0 .. 32768),
        PCmdToMAB(15:15..15): BOOLEAN,
        fill16(16:0..14): [0 .. 32768),
        MCmdIn(16:15..15): BOOLEAN,
        fill17(17:0..14): [0 .. 32768),
        MCmdOutAB(17:15..15): BOOLEAN,
        fill18(18:0..14): [0 .. 32768),
        MCmdDriveC(18:15..15): BOOLEAN,
        fill19(19:0..14): [0 .. 32768),
        MDataI(19:15..15): BOOLEAN,
        fill20(20:0..14): [0 .. 32768),
        MParityI(20:15..15): BOOLEAN,
        fill21(21:0..14): [0 .. 32768),
        MDataDriveC(21:15..15): BOOLEAN,
        fill22(22:0..14): [0 .. 32768),
        MSharedSense(22:15..15): BOOLEAN,
        fill23(23:0..14): [0 .. 32768),
        MNSharedDriveHighC(23:15..15): BOOLEAN,
        fill24(24:0..14): [0 .. 32768),
        MNSharedDriveLowC(24:15..15): BOOLEAN,
        fill25(25:0..14): [0 .. 32768),
        MNErrorDriveLow(25:15..15): BOOLEAN,
        fill26(26:0..14): [0 .. 32768),
        MRqIBA(26:15..15): BOOLEAN,
        fill27(27:0..14): [0 .. 32768),
        MNewRqIBA(27:15..15): BOOLEAN,
        fill28(28:0..14): [0 .. 32768),
        MNewRqEnableC(28:15..15): BOOLEAN,
        fill29(29:0..14): [0 .. 32768),
        MGntSenseA(29:15..15): BOOLEAN,
        fill30(30:0..14): [0 .. 32768),
        SuppressPSampleAB(30:15..15): BOOLEAN,
        fill31(31:0..14): [0 .. 32768),
        MIsDoneAB(31:15..15): BOOLEAN,
        fill32(32:0..14): [0 .. 32768),
        SetWantWSA(32:15..15): BOOLEAN,
        fill33(33:0..14): [0 .. 32768),
        CheckFaultsAB(33:15..15): BOOLEAN,
        fill34(34:0..14): [0 .. 32768),
        SenseSharedB(34:15..15): BOOLEAN,
        fill35(35:0..14): [0 .. 32768),
        ReleaseMBusBA(35:15..15): BOOLEAN,
        fill36(36:0..14): [0 .. 32768),
        ForceIdleAB(36:15..15): BOOLEAN,
        fill37(37:0..14): [0 .. 32768),
        DoneAB(37:15..15): BOOLEAN,
        fill38(38:0..14): [0 .. 32768),
        ForceSlaveBA(38:15..15): BOOLEAN,
        fill39(39:0..14): [0 .. 32768),
        SenseReadyBA(39:15..15): BOOLEAN,
        fill40(40:0..14): [0 .. 32768),
        MDataIToFaultsB(40:15..15): BOOLEAN,
        fill41(41:0..14): [0 .. 32768),
        MapBitsToMDataIA(41:15..15): BOOLEAN,
        fill42(42:0..14): [0 .. 32768),
        ACheckParityA(42:15..15): BOOLEAN,
        fill43(43:0..14): [0 .. 32768),
        BCheckParityB(43:15..15): BOOLEAN,
        fill44(44:0..14): [0 .. 32768),
        SampleRealMatchA(44:15..15): BOOLEAN,
        fill45(45:0..14): [0 .. 32768),
        MCmdDriveA(45:15..15): BOOLEAN,
        fill46(46:0..14): [0 .. 32768),
        MDataDriveA(46:15..15): BOOLEAN,
        fill47(47:0..14): [0 .. 32768),
        DriveSharedHighA(47:15..15): BOOLEAN,
        fill48(48:0..14): [0 .. 32768),
        DriveSharedLowA(48:15..15): BOOLEAN,
        fill49(49:0..14): [0 .. 32768),
        MasterEnableMBusDriveAB(49:15..15): BOOLEAN,
        fill50(50:0..14): [0 .. 32768),
        MCmdDriveToDataTransportAB(50:15..15): BOOLEAN,
        fill51(51:0..14): [0 .. 32768),
        MCmdDriveToNoOpAB(51:15..15): BOOLEAN,
        fill52(52:0..14): [0 .. 32768),
        GetAdrCmdBA(52:15..15): BOOLEAN,
        fill53(53:0..14): [0 .. 32768),
        IsCleanBA(53:15..15): BOOLEAN,
        fill54(54:0..14): [0 .. 32768),
        LatchSharedBA(54:15..15): BOOLEAN,
        fill55(55:0..14): [0 .. 32768),
        MasterBA(55:15..15): BOOLEAN,
        fill56(56:0..14): [0 .. 32768),
        MatchRealQuadAB(56:15..15): BOOLEAN,
        fill57(57:0..14): [0 .. 32768),
        MatchRealBlockAB(57:15..15): BOOLEAN,
        fill58(58:0..14): [0 .. 32768),
        ContinueBA(58:15..15): BOOLEAN,
        fill59(59:0..14): [0 .. 32768),
        OneDirtyBA(59:15..15): BOOLEAN,
        fill60(60:0..14): [0 .. 32768),
        SomeDirtyBA(60:15..15): BOOLEAN,
        fill61(61:0..14): [0 .. 32768),
        MDataDriveDelayedA(61:15..15): BOOLEAN,
        fill62(62:0..14): [0 .. 32768),
        ROMSequenceBA(62:15..15): BOOLEAN,
        fill63(63:0..14): [0 .. 32768),
        ROMSlaveBA(63:15..15): BOOLEAN,
        fill64(64:0..14): [0 .. 32768),
        ROMCycleBA(64:15..15): BOOLEAN,
        fill65(65:0..14): [0 .. 32768),
        MRamRegParityOut(65:15..15): BOOLEAN];


    CreateMSequencerIO: PROC [cell: Cell] --IOCreator-- = {
        cell.realCellStuff.newIO _ NEW [MSequencerIORec];
        cell.realCellStuff.oldIO _ NEW [MSequencerIORec];
        };

    MSequencerStateRef: TYPE = REF MSequencerStateRec;
    MSequencerStateRec: TYPE = RECORD [
    PhALast, PhC: BOOL, -- hacks to emulate A rise to B fall strobes
    MCmdDriveEnable, MDataDriveEnable, DriveSharedHighEnable, DriveSharedLowEnable: BOOL,
    MIdleAB, MIdleBA, HoldingAB, HoldingBA: BOOL,
    MGntAB, MGntBA, MRqAB, NewRqAB, NewRqBA: BOOL,
    CurrentPDemandsAB, CurrentPDemandsBA: BitWord,
    CurrentSequenceBA, CycleShifterAB: BitWord,
    HoldTypeBA, NotHoldTypeBA, DidRMBA, DirtyPageBA: BOOL,
    IODoneCommandBA, ForceSlave, ParityAB, ParityBA: BOOL,
    CmdOutBA: MBusCommands,
    FaultBitsBA: PBusFaults,
    <<Intermediate values, not really state bits>>
    PWantsM, EnableMBusDrive, ZapABit, EarlyIdleAB, ReallySuppressPSampleAB: BOOL,
    CmdOutAB: MBusCommands
        ];

    InitializeMSequencer: Initializer = {
        IF leafily THEN
            BEGIN
            state: MSequencerStateRef _ NEW [MSequencerStateRec];
            cell.realCellStuff.state _ state;
            END;
        };

    MSequencerEvalSimple: CellProc =
        BEGIN
        newIO: MSequencerIORef _ NARROW[cell.realCellStuff.newIO];
        state: MSequencerStateRef _ NARROW[cell.realCellStuff.state];
            BEGIN OPEN newIO, state;
            IF PhBb THEN PhALast _ FALSE;
            IF PhAb THEN PhALast _ TRUE;
            PhC _ PhAb OR PhBb OR PhALast;
            EarlyIdleAB _ MGntAB AND DoneAB AND ECFW[CurrentPDemandsAB, 7, 0, 4]=1;
            ReallySuppressPSampleAB _ SuppressPSampleAB OR EarlyIdleAB;

            <<Master sequencer>>

            {
            sample: BOOL _ MIdleAB AND NOT ReallySuppressPSampleAB;
            store: BOOL _ PCmdToMAB=Store OR PCmdToMAB=StoreHold;
            fetchOrStore: BOOL _ PCmdToMAB=Fetch OR PCmdToMAB=FetchHold OR store;
            ioFetch: BOOL _ PCmdToMAB=IOFetch OR PCmdToMAB=IOFetchHold;
            ioStore: BOOL _ PCmdToMAB=IOStore OR PCmdToMAB=IOStoreHold;
            PWantsM _ ((fetchOrStore AND nVQMatchB) OR (store AND ((NOT nQuadSharedB) OR nPageDirtyB)) OR ioFetch OR ioStore OR 
            PCmdToMAB=StoreHold OR PCmdToMAB=FetchHold) AND NOT ReallySuppressPSampleAB;

            ZapABit _ PhAb AND MIsDoneAB AND (NOT EBFW[CurrentPDemandsBA, 7, 0] OR OneDirtyBA);
            Assert[NOT MoreThanOneOf[ZapABit, SetWantWSA]];
            IF PhAb THEN CurrentPDemandsAB _ CurrentPDemandsBA;
            IF ZapABit THEN FOR i:CARDINAL IN [0..5] DO
            IF EBFW[CurrentPDemandsBA, 7, i] THEN {
            CurrentPDemandsAB _ IBIW[FALSE, CurrentPDemandsBA, 7, i];
            EXIT;
            };
            ENDLOOP;
            IF SetWantWSA THEN CurrentPDemandsAB _ IBIW[store AND LatchSharedBA, CurrentPDemandsBA, 7, 3];
            IF PhAb AND CheckFaultsAB AND FaultBitsBA#Dragon.None THEN CurrentPDemandsAB _ 1;

            IF PhBb AND NOT sample THEN CurrentPDemandsBA _ CurrentPDemandsAB;
            IF PhBb AND sample THEN {
            CurrentPDemandsBA _ IBIW[TRUE, 0, 7, 6]; -- start with only idle required.
            IF fetchOrStore AND nVirtualBlockMatchB AND SomeDirtyBA THEN CurrentPDemandsBA _ IBIW[TRUE, CurrentPDemandsBA, 7, 0];
            IF (fetchOrStore AND nMapValidB) OR (store AND nPageDirtyB) THEN CurrentPDemandsBA _ IBIW[TRUE, CurrentPDemandsBA, 7, 1];
            IF fetchOrStore AND nVQMatchB THEN CurrentPDemandsBA _ IBIW[TRUE, CurrentPDemandsBA, 7, 2];
            IF store AND NOT nQuadSharedB THEN CurrentPDemandsBA _ IBIW[TRUE, CurrentPDemandsBA, 7, 3];
            IF ioFetch THEN CurrentPDemandsBA _ IBIW[TRUE, CurrentPDemandsBA, 7, 4];
            IF ioStore THEN CurrentPDemandsBA _ IBIW[TRUE, CurrentPDemandsBA, 7, 5];
            HoldTypeBA _ PCmdToMAB=StoreHold OR PCmdToMAB=FetchHold OR PCmdToMAB=IOFetchHold OR PCmdToMAB=IOStoreHold;
            NotHoldTypeBA _ NOT (PCmdToMAB=NoOp OR PCmdToMAB=StoreHold OR PCmdToMAB=FetchHold OR PCmdToMAB=IOFetchHold OR 
            PCmdToMAB=IOStoreHold);
            DidRMBA _ fetchOrStore AND nMapValidB;
            DirtyPageBA _ store AND (nMapValidB OR nPageDirtyB);
            IsCleanBA _ nPageDirtyB AND NOT DirtyPageBA;
            };
            };
            IF SenseSharedB THEN LatchSharedBA _ MSharedSense;
            IF PhAb THEN nVQMatchB _ nQuadSharedB _ nPageDirtyB _ nMapValidB _ nVirtualBlockMatchB _ TRUE;
            IF PhBb THEN nRQMatchA _ nRealBlockMatchA _ TRUE;
            IF PhAb THEN MDoneAB _ MIsDoneAB AND (ECFW[CurrentPDemandsAB, 7, 0, 6]=0 OR (CheckFaultsAB AND FaultBitsBA#Dragon.None));
            <<>>
            <<Bus arbitration>>
            <<>>
            <<MIdleAB indicates that the low level M controller has finished with the last request from P that caused it to become active and 
            so the M bus should be given up.>>
            <<Holding indicates that a series of XHold commands are in progress on P and so the M bus should not be given up.>>
            <<>>
            IF PhBb THEN {
            fault: BOOL _ CheckFaultsAB AND FaultBitsBA#Dragon.None;
            HoldingBA _ HoldingAB AND NOT fault;
            MIdleBA _ IF (ReleaseMBusBA AND ECFW[CurrentPDemandsAB, 7, 0, 6]=0) OR EarlyIdleAB OR fault THEN TRUE ELSE MIdleAB;
            MGntBA _ MGntAB;
            MNewRqIBA _ (NOT NewRqAB) AND MIdleBA AND PWantsM AND MRqAB AND (NOT HoldingBA);
            NewRqBA _ NewRqAB;
            MRqIBA _ NOT MIdleBA OR PWantsM OR HoldingBA;
            };
            IF PhAb THEN {
            wonArbitration: BOOL _ MGntSenseA AND (NOT MGntBA OR NewRqBA); 
            MRqAB _ MRqIBA;
            MGntAB _ MGntSenseA;
            MIdleAB _ IF (wonArbitration OR HoldingBA) AND NOT ECFW[CurrentPDemandsBA, 7, 0, 6]=0 THEN FALSE ELSE MIdleBA;
            HoldingAB _ IF wonArbitration AND HoldTypeBA THEN TRUE ELSE IF NotHoldTypeBA THEN FALSE ELSE HoldingBA;
            MHeldAB _ HoldingBA AND HoldingAB;
            NewRqAB _ MNewRqIBA;
            };
            MNewRqEnableC _ PhC AND MGntBA;

            <<Current sequence>>

            {
            prioritySequence: BitWord _ BitWordZero;
            slaveSequence: BitWord _ IF ForceIdleAB THEN 1 ELSE SELECT MCmdIn FROM
            ReadQuad => 020H,
            WriteQuad => 010H,
            WriteSingle => 08H,
            ChangeFlags => 04H,
            IOReadDone, IOWriteDone, DataTransport, IORead, IOWrite, Reserve9, Reserve10, Reserve11, Reserve12, Reserve13, Reserve14, NoOp => 
            01H,
            ENDCASE => ERROR;
            FOR i:CARDINAL IN [0..6] DO
            IF EBFW[CurrentPDemandsAB, 7, i] THEN {
            prioritySequence _ IBIW[TRUE, 0, 7, i];
            EXIT;
            };
            ENDLOOP;
            CmdOutAB _ SELECT prioritySequence FROM
            040H => WriteQuad,
            020H => IORead,
            010H => ReadQuad,
            008H => WriteSingle,
            004H => IORead,
            002H => IOWrite,
            001H => NoOp,
            ENDCASE => NoOp;
            IF PhBb AND DoneAB THEN CurrentSequenceBA _ IF MGntAB THEN prioritySequence ELSE slaveSequence;
            IF PhBb THEN {
            GetAdrCmdBA _ SELECT prioritySequence FROM
            040H => VictimReal,
            020H => RefVirtual,
            010H => IF DidRMBA THEN RefRealMap ELSE RefRealAssemble,
            008H => RefRealAssemble,
            004H => RefVirtual,
            002H => RefVirtual,
            001H => RefVirtual,
            ENDCASE => RefVirtual;
            };
            };
            IF PhAb THEN MCmdOutAB _ SELECT TRUE FROM
            MCmdDriveToDataTransportAB => DataTransport,
            MCmdDriveToNoOpAB => NoOp,
            ENDCASE => CmdOutBA;
            IF PhBb THEN {
            CmdOutBA _ CmdOutAB;
            IODoneCommandBA _ MCmdIn=IOReadDone OR MCmdIn=IOWriteDone;
            };
            ROMSequenceBA _ IF (ForceSlaveBA AND NOT IODoneCommandBA) OR Resetb THEN 1 ELSE CurrentSequenceBA;

            <<Slave control>>
            <<>>
            IF ForceSlaveBA THEN ForceSlave _ TRUE;
            IF PhBb THEN ROMSlaveBA _ IF ForceSlave AND NOT IODoneCommandBA THEN TRUE ELSE NOT MGntAB;
            Assert[NOT MoreThanOneOf[ForceSlaveBA, IODoneCommandBA]];
            IF PhAb AND IODoneCommandBA THEN ForceSlave _ FALSE;
            IF PhBb THEN MasterBA _ MGntBA AND NOT ForceSlave;
            <<>>
            <<Cycle control>>

            IF PhBb THEN ContinueBA _ NOT SenseReadyBA OR MCmdIn=DataTransport;
            IF Resetb THEN ROMCycleBA _ 20H ELSE IF PhBb THEN ROMCycleBA _ SELECT TRUE FROM
            NOT DoneAB AND NOT ContinueBA => CycleShifterAB,
            NOT DoneAB AND ContinueBA => WShift[CycleShifterAB, 7, -1],
            DoneAB AND NOT (ForceSlave AND IODoneCommandBA) => IBIW[TRUE, 0, 7, 1],
            DoneAB AND (ForceSlave AND IODoneCommandBA) => IBIW[TRUE, 0, 7, 2],
            ENDCASE => ERROR;
            IF PhAb THEN CycleShifterAB _  ROMCycleBA;

            <<Fault and Map Bits>>

            IF MDataIToFaultsB THEN FaultBitsBA _ LOOPHOLE[ECFD[MDataI, 32, 29, 3]];
            IF PhAb THEN MFaultAB _ IF CheckFaultsAB THEN FaultBitsBA ELSE Dragon.None;
            IF MapBitsToMDataIA THEN {
            MDataI _ IBID[DidRMBA, MDataI, 32, 24];  -- read the map
            MDataI _ IBID[DirtyPageBA, MDataI, 32, 25];  -- set the dirty bit
            MDataI _ ICID[0, MDataI, 32, 26, 6];  -- zero the rest of the bits
            };

            <<Parity>>

            IF BCheckParityB THEN ParityBA _ MRamRegParityOut AND (MatchRealQuadAB OR MasterEnableMBusDriveAB);
            IF PhAb AND ParityBA THEN MNErrorDriveLow _ TRUE;
            IF ACheckParityA THEN ParityAB _ MRamRegParityOut AND ContinueBA;
            IF PhBb AND ParityAB THEN MNErrorDriveLow _ TRUE;

            <<M bus control>>

            EnableMBusDrive _ MatchRealQuadAB OR MasterEnableMBusDriveAB;
            IF SampleRealMatchA THEN {
            MatchRealQuadAB _ NOT nRQMatchA;
            MatchRealBlockAB _ NOT nRealBlockMatchA;
            };
            IF NOT PhC THEN MCmdDriveEnable _ MDataDriveEnable _ DriveSharedHighEnable _ DriveSharedLowEnable _ FALSE;
            IF MCmdDriveA AND EnableMBusDrive THEN MCmdDriveEnable _ TRUE;
            IF (MDataDriveA AND EnableMBusDrive) OR MDataDriveDelayedA THEN MDataDriveEnable _ TRUE;
            IF DriveSharedHighA THEN DriveSharedHighEnable _ TRUE;
            IF DriveSharedLowA AND EnableMBusDrive THEN DriveSharedLowEnable _ TRUE;
            MCmdDriveC _ PhC AND MCmdDriveEnable;
            MDataDriveC _ PhC AND MDataDriveEnable;
            MNSharedDriveHighC _ PhC AND DriveSharedHighEnable;
            MNSharedDriveLowC _ PhC AND DriveSharedLowEnable;

            <<Reset>>

            IF Resetb THEN {
            HoldingAB _ FALSE;
            MIdleAB _ TRUE;
            MNErrorDriveLow _ FALSE;
            ForceSlave _ FALSE;
            };

            END;
        END;

    RegisterCells[];

    END.