CacheMInterfaceMRAMDriver.rose
Last edited by: Barth, July 26, 1984 5:25:41 pm PDT
Last edited by: Curry, January 29, 1985 9:30:00 pm PST
Imports BitOps, BitSwOps, CacheOps, Dragon;
Open BitOps, BitSwOps, Dragon;
CELLTYPE "MRAMDriver"
PORTS[
Timing and housekeeping interface
Vdd, Gnd<BOOL,
Buffered timing and housekeeping interface
nPhBb<BOOL,
RAM access
PBitsB, nPBitsB=SWITCH[132]-(Special XPhobic),
MBitsA, nMBitsA=SWITCH[132]-(Special XPhobic),
P control <=> M control
PAdr2831AB<INT[4],
Internal main memory interface
MDataI=INT[32],
MParityI=BOOL,
RAM ROM interface
DriveMBitsA, DriveMBitsNoMatchA, SenseMBitsA, DriveMDataIA, SenseMDataIB, DrivePBitsB, SensePBitsB<BOOL,
Control steel wool
MatchRealQuadAB<BOOL,
MDataDriveDelayedA<BOOL,
MAdr3031BA<INT[2],
MRamRegParityOut>BOOL
]
State
MRAMReg: BitDWord,
MRAMRegParity: BOOL
EvalSimple
Assert[NOT MoreThanOneOf[DriveMBitsA, SenseMBitsA]];
Assert[NOT MoreThanOneOf[DriveMDataIA, SenseMDataIB]];
Assert[NOT MoreThanOneOf[DrivePBitsB, SensePBitsB]];
Assert[NOT MoreThanOneOf[SenseMBitsA, SenseMDataIB, SensePBitsB]];
TRUSTED {
offset: CARDINAL ← ECFW[MAdr3031BA, 2, 0, 2];
mbitd: SwitchMWord ← DESCRIPTOR[MBitsA];
nmbitd: SwitchMWord ← DESCRIPTOR[nMBitsA];
IF SenseMDataIB THEN {
MRAMReg ← MDataI;
MRAMRegParity ← MParityI;
};
CacheOps.DriveBus[mbitd, nmbitd, DriveMBitsA OR (DriveMBitsNoMatchA AND NOT MatchRealQuadAB), offset, MRAMReg, MRAMRegParity];
IF NOT nPhBb THEN {
FOR j:CARDINAL IN [0..4) DO
SCDTS[BitDWordOnes, 32, 0, 32, mbitd, 132, j*32, 32, [[none, X], [drive, H]]];
SCDTS[BitDWordOnes, 32, 0, 32, nmbitd, 132, j*32, 32, [[none, X], [drive, H]]];
ENDLOOP;
SCWTS[BitWordOnes, 16, 0, 4, mbitd, 132, 128, 4, [[none, X], [drive, H]]];
SCWTS[BitWordOnes, 16, 0, 4, nmbitd, 132, 128, 4, [[none, X], [drive, H]]];
};
IF SenseMBitsA THEN {
FOR i:CARDINAL IN [0..32) DO
MRAMReg ← IBID[EBFS[mbitd, 132, (4*i)+offset], MRAMReg, 32, i];
ENDLOOP;
MRAMRegParity ← EBFS[mbitd, 132, 128+offset];
};
};
IF DriveMDataIA OR MDataDriveDelayedA THEN {
MDataI ← MRAMReg;
MParityI ← MRAMRegParity;
};
TRUSTED {
offset: CARDINAL ← ECFW[PAdr2831AB, 4, 2, 2];
pbitd: SwitchMWord ← DESCRIPTOR[PBitsB];
npbitd: SwitchMWord ← DESCRIPTOR[nPBitsB];
CacheOps.DriveBus[pbitd, npbitd, DrivePBitsB, offset, MRAMReg, MRAMRegParity];
IF SensePBitsB THEN {
FOR i:CARDINAL IN [0..32) DO
MRAMReg ← IBID[EBFS[pbitd, 132, (4*i)+offset], MRAMReg, 32, i];
ENDLOOP;
MRAMRegParity ← EBFS[pbitd, 132, 128+offset];
};
};
MRamRegParityOut ← CacheOps.Parity32[LOOPHOLE[MRAMReg]];
IF MRAMRegParity THEN MRamRegParityOut ← NOT MRamRegParityOut;
ENDCELLTYPE