PhA, PhB<BOOL,

Vdd, Gnd<BOOL,

PadVdd, PadGnd<BOOL,

MCmdAB=EnumType["Dragon.MBusCommands"],

MDataAB=INT[32],

MParityAB=BOOL,

MNShared=BOOL,

MNError>BOOL,

MRq>BOOL,

MNewRq>BOOL,

MGnt<BOOL,

All the following signals change during PhA and propagate during the remainder of PhA and PhB, giving an entire clock cycle for them to propagate throughout the machine. Each user must receive them into a latch open during PhB. The effects of changes are intended to happen throughout the following PhA, PhB pair.

ResetAB<BOOL,

DHoldAB<BOOL, -- must be high before testing

DShiftAB<BOOL, -- shift the shift register by 1 bit if ~DNSelect

DExecuteAB<BOOL, -- interpret the content of the shift register if ~DNSelect

DNSelectAB<BOOL, -- if high, hold but don't Execute or Shift

DDataInAB<BOOL, -- sampled during each PhB that DShift is asserted

DDataOutAB=BOOL, -- changes during each PhA following a PhB that DShift is asserted, continues to be driven through the PhB following the PhA it changes

PhAb, nPhAb, PhBb, nPhBb>BOOL,

Resetb>BOOL,

MCmdIn>EnumType["Dragon.MBusCommands"],

MCmdOutAB<EnumType["Dragon.MBusCommands"],

MCmdDriveC<BOOL,

MDataI=INT[32],

MParityI=BOOL,

MDataDriveC<BOOL,

MSharedSense>BOOL,

MNSharedDriveHighC<BOOL,

MNSharedDriveLowC<BOOL,

MNErrorDriveLow<BOOL,

MRqIBA<BOOL,

MNewRqIBA<BOOL,

MNewRqEnableC<BOOL,

MGntSenseA>BOOL

MPadRegAB: BitDWord,

MPadRegParityAB: BOOL

PhAb ← PhA;

nPhAb ← NOT PhA;

PhBb ← PhB;

nPhBb ← NOT PhB;

Resetb ← ResetAB;

IF MCmdDriveC THEN MCmdAB ← MCmdOutAB;

MCmdIn ← MCmdAB;

IF PhAb THEN {

IF PhBb THEN {

IF MDataDriveC THEN {

MSharedSense ← NOT MNShared;

IF MNSharedDriveHighC THEN MNShared ← TRUE;

IF MNSharedDriveLowC THEN MNShared ← FALSE;

IF MNErrorDriveLow THEN MNError ← FALSE;

MRq ← MRqIBA;

IF MNewRqEnableC THEN MNewRq ← MNewRqIBA;

MGntSenseA ← MGnt;