<> <> <> Imports BitOps, BitSwOps; Open BitOps, BitSwOps; CELLTYPE "MCAMDriver" PORTS[ <> Vdd, Gnd> <> PhAb, PhBb> CAMPage, nCAMPage=SWITCH[24]-(Special XPhobic), CAMBlock, nCAMBlock=SWITCH[4]-(Special XPhobic), <<>> <> MDataI=INT[32], <> CAMRegSenseMDataIB, ACAMRegDriveCAMBitsA, BCAMRegDriveCAMBitsAB, FormAddressBA, PageDriveMDataIA, BlockDriveMDataIA> GetAdrCmdBA> PageRegSenseCAMBitsA, BlockRegSenseCAMBitsA, PrechargeCAMBits, DriveCAMBits: BOOL EvalSimple BlockRegSenseCAMBitsA _ PhAb AND FormAddressBA AND MasterBA; PrechargeCAMBits _ PhBb AND FormAddressBA AND MasterBA; DriveCAMBits _ (PhBb AND ((FormAddressBA AND NOT MasterBA) OR BCAMRegDriveCAMBitsAB)) OR ACAMRegDriveCAMBitsA; PageRegSenseCAMBitsA _ BlockRegSenseCAMBitsA AND (GetAdrCmdBA=VictimReal OR GetAdrCmdBA=RefRealAssemble OR GetAdrCmdBA=RefVirtual); IF CAMRegSenseMDataIB THEN { PageReg _ MDTD[MDataI, 32, 0, 24, PageReg, 24, 0, 24]; BlockReg _ MDTW[MDataI, 32, 24, 4, BlockReg, 4, 0, 4]; }; TRUSTED { cpd: SwitchMWord _ DESCRIPTOR[CAMPage]; ncpd: SwitchMWord _ DESCRIPTOR[nCAMPage]; cbd: SwitchMWord _ DESCRIPTOR[CAMBlock]; ncbd: SwitchMWord _ DESCRIPTOR[nCAMBlock]; s: SwitchTypes.Strength _ IF DriveCAMBits THEN driveStrong ELSE none; IF PageRegSenseCAMBitsA THEN PageReg _ CSTD[cpd, 24, 0, 24, PageReg, 24, 0, 24]; IF BlockRegSenseCAMBitsA THEN BlockReg _ CSTW[cbd, 4, 0, 4, BlockReg, 4, 0, 4]; SCDTS[PageReg, 24, 0, 24, cpd, 24, 0, 24, [[s, L], [s, H]]]; SCDTS[PageReg, 24, 0, 24, ncpd, 24, 0, 24, [[s, H], [s, L]]]; SCWTS[BlockReg, 4, 0, 4, cbd, 4, 0, 4, [[s, L], [s, H]]]; SCWTS[BlockReg, 4, 0, 4, ncbd, 4, 0, 4, [[s, H], [s, L]]]; IF PrechargeCAMBits THEN { SCDTS[BitDWordOnes, 24, 0, 24, cpd, 24, 0, 24, [[none, X], [drive, H]]]; SCDTS[BitDWordOnes, 24, 0, 24, ncpd, 24, 0, 24, [[none, X], [drive, H]]]; SCWTS[BitWordOnes, 4, 0, 4, cbd, 4, 0, 4, [[none, X], [drive, H]]]; SCWTS[BitWordOnes, 4, 0, 4, ncbd, 4, 0, 4, [[none, X], [drive, H]]]; }; }; IF PageDriveMDataIA THEN MDataI _ MDTD[PageReg, 24, 0, 24, MDataI, 32, 0, 24]; IF BlockDriveMDataIA THEN MDataI _ MWTD[BlockReg, 4, 0, 4, MDataI, 32, 24, 4]; ENDCELLTYPE