CacheMCtlROM.rose
Last edited by: Barth, June 21, 1984 9:07:45 pm PDT
Directory BitOps;
Open BitOps;
MCtlROM: CELL[
Timing and housekeeping interface
Vdd, Gnd<BOOL,
LatchBias<BOOL,
Buffered timing and housekeeping interface
PhAb, PhBb<BOOL,
Resetb<BOOL,
Cell control
FinishSharedStore>BOOL,
SenseRMatch, SelOrphanAdr, SelVP, SelPageFlags>BOOL,
Entry Control ROM interface
SetSharedA, SetRPDirtyVPValidA, FlagLatchB, ResetVPValidA, SetFlagsA, ResetMasterA, IncrementRefreshB, IncrementVictimB, SampleDirtyBitsB, DeleteDirtyBitB, VictimToDecoderBA, RefreshToDecoderBA, IfGrantThenGetAdrElseRefreshToDecoderBA, DirtyBitsToMQSelBA, SamplePAdr2829B, SampleMAdr2829B, Adr2829ToMQSelBA, AddressBitsToMDataIA, AddressBitsLowZeroToMDataIA, SelectRPBA, SelectRealDataBA>BOOL,
]
State
EvalSimple
ENDCELL;