<> <> MCtlRAMCtl: CELL[ <> Vdd, Gnd> <> PhBb M control>> PAdrHigh> DoHoldBA> <> ShiftDataToMCtl> <> nMBitsPrecharge, MuxRight, MuxLeft, MBitsDrive, nMBitsDrive, MRamRegToMDataI, nMRamRegToMDataI, SenseMBits, SenseMDataI, ParityIn>BOOL, SensePBitsLeft, SensePBitsRight, DrivePBits, nDrivePBits>BOOL, MRamRegToMBits, nMRamRegToMBits>BOOL, ShiftToMBits, nShiftToMBits, MBitsToShift, nMBitsToShift>BOOL, <> ShiftDataToFlagCtl>BOOL, ReadEntry, WriteEntry> RAMMDataIToMRAMReg, RAMMBitsToMRAMReg, RAMMRAMRegToMDataI, RAMMRAMRegToMBits, RAMMRAMRegToMBitsNoOrphan, RAMPBitsToMRAMReg, RAMLeftPBitsToMRAMReg, RAMMRAMRegToPBits> MatchRealBA, MAdrHigh