CacheMCtlRAMCtl.rose
Last edited by: Barth, June 21, 1984 3:47:17 pm PDT
MCtlRAMCtl: CELL[
Timing and housekeeping interface
Vdd, Gnd<BOOL,
LatchBias<BOOL,
Buffered timing and housekeeping interface
PhBb<BOOL,
P control <=> M control
PAdrHigh<BOOL,
Debug interface
DoHoldBA<BOOL,
More debug interface
ShiftDataToMCtl<BOOL,
ShiftEqual, nShiftEqual, ShiftFeedBack, nShiftFeedBack, ShiftShift, nShiftShift<BOOL,
MRAMDriver interface
nMBitsPrecharge, MuxRight, MuxLeft, MBitsDrive, nMBitsDrive, MRamRegToMDataI, nMRamRegToMDataI, SenseMBits, SenseMDataI, ParityIn>BOOL,
SensePBitsLeft, SensePBitsRight, DrivePBits, nDrivePBits>BOOL,
MRamRegToMBits, nMRamRegToMBits>BOOL,
ShiftToMBits, nShiftToMBits, MBitsToShift, nMBitsToShift>BOOL,
Still more debug interface
ShiftDataToFlagCtl>BOOL,
ReadEntry, WriteEntry<BOOL,
ShiftExecute, nShiftExecute<BOOL,
RAM control interface
RAMMDataIToMRAMReg, RAMMBitsToMRAMReg, RAMMRAMRegToMDataI, RAMMRAMRegToMBits, RAMMRAMRegToMBitsNoOrphan, RAMPBitsToMRAMReg, RAMLeftPBitsToMRAMReg, RAMMRAMRegToPBits<BOOL,
Control steel wool
MatchRealBA, MAdrHigh<BOOL
]
State
shiftHighAddress, nshiftHighAddress: BOOL,
MAdrCtrAB, MAdrCtrBA: CARDINAL
EvalSimple
IF IncrementMAdrCtrB THEN MAdrCtrBA ← (MAdrCtrAB+1) MOD 4;
IF PhAb THEN {
MAdrCtrAB ← MAdrCtrBA;
};
IF LoadMAdrCtrFromMDataIB THEN MAdrCtrBA ← ECFD[MDataI, 32, 30, 2];
IF ZeroMAdrCtrB THEN MAdrCtrBA ← 0;
IF LoadMAdrCtrFromPAdrB THEN MAdrCtrBA ← MWTW[PAdrAB, 4, 2, 2, MAdrCtrBA, 2, 0, 2];
nMBitsPrecharge ← NOT PhBb;
MuxLeft ← IF DoHoldBA THEN shiftHighAddress ELSE NOT MAdrHigh;
MuxRight ← NOT MuxLeft;
MRamRegToMBits ← (RAMMRAMRegToMBits OR (RAMMRAMRegToMBitsNoOrphan AND NOT MatchRealBA));
nMRamRegToMBits ← NOT MRamRegToMBits;
ShiftToMBits ← ShiftExecute AND WriteEntry;
nShiftToMBits ← NOT ShiftToMBits;
MBitsDrive ← MRamRegToMBits OR ShiftToMBits;
nMBitsDrive ← NOT MBitsDrive;
MRamRegToMDataI ← RAMMRAMRegToMDataI;
nMRamRegToMDataI ← NOT MRamRegToMDataI;
SenseMBits ← RAMMBitsToMRAMReg;
SenseMDataI ← RAMMDataIToMRAMReg;
ParityIn ← FALSE;
SensePBitsLeft ← RAMLeftPBitsToMRAMReg OR (RAMPBitsToMRAMReg AND NOT PAdrHigh);
SensePBitsRight ← RAMPBitsToMRAMReg AND PAdrHigh;
DrivePBits ← RAMMRAMRegToPBits;
nDrivePBits ← NOT RAMMRAMRegToPBits;
MBitsToShift ← ShiftExecute AND ReadEntry;
nMBitsToShift ← NOT MBitsToShift;
IF ShiftShift THEN nshiftHighAddress ← NOT ShiftDataToMCtl;
IF ShiftFeedBack THEN nshiftHighAddress ← NOT shiftHighAddress;
IF ShiftEqual THEN shiftHighAddress ← NOT nshiftHighAddress;
ShiftDataToFlagCtl ← shiftHighAddress;
ENDCELL