CacheMCtlEntryCtl.rose
Last edited by: Barth, June 21, 1984 9:10:39 pm PDT
Directory CacheOps;
Imports BitOps, BitSwOps, Dragon;
Open BitOps, BitSwOps, Dragon;
MCtlEntryCtl: CELL[
Timing and housekeeping interface
Vdd, Gnd<BOOL,
LatchBias<BOOL,
Buffered timing and housekeeping interface
PhAb, PhBb<BOOL,
Resetb<BOOL,
Cell control
QValidA, nQValidA, QSharedA, nQSharedA, QMasterA, nQMasterA=BIT-S-X,
MQSelBA>INT[4], nQDirtyB=INT[4],
RPValidBitA, nRPValidBitA, RPDirtyBitA, nRPDirtyBitA, VPValidBitA, nVPValidBitA=BIT-S-X,
ForceAllDataSelectsBA>BOOL,
CellAdrBA, nCellAdrBA>INT[7],
SelMapAdrBA, SelRPBA, SelRealDataBA>BOOL,
P control <=> M control
PAdr2829AB<INT[4],
Internal main memory interface
MDataI=INT[32],
Entry Control ROM interface
SetSharedA, SetRPDirtyVPValidA, FlagLatchB, ResetVPValidA, SetFlagsA, ResetMasterA, IncrementRefreshB, IncrementVictimB, SampleDirtyBitsB, DeleteDirtyBitB, VictimToDecoderBA, RefreshToDecoderBA, IfGrantThenGetAdrElseRefreshToDecoderBA, DirtyBitsToMQSelBA, SamplePAdr2829B, SampleMAdr2829B, Adr2829ToMQSelBA, AddressBitsToMDataIA, AddressBitsLowZeroToMDataIA, SelectRPBA, SelectRealDataBA<BOOL,
Control steel wool
GetAdrCmdBA<EnumType["CacheOps.PreFetchAdrCmd"],
IsCleanBA, LatchSharedBA, MGntSenseBA<BOOL,
SomeDirtyBA>BOOL
]
State
RefreshCountAB, RefreshCountBA: CARDINAL,
VictimCountAB, VictimCountBA: CARDINAL,
LatchVPValidBA, LatchRPDirtyBA: BOOL,
VictimDirtyBitsAB, VictimDirtyBitsBA: BitWord,
Adr2829BA: CARDINAL,
Intermediate values, not actual state bits
DoGetAdrBA, DoRefreshBA: BOOL
EvalSimple
DriveBit: PROC[bit, nBit: Switch, dBit: BOOL] RETURNS [newBit, newNBit: Switch] = {
newBit ← SIBISS[dBit, bit, [[driveStrong, L], [driveStrong, H]]];
newNBit ← SIBISS[dBit, nBit, [[driveStrong, H], [driveStrong, L]]];
};
{
s: SwitchTypes.Strength ← IF PhBb THEN drive ELSE none;
VPValidBitA ← SIBISS[TRUE, VPValidBitA, [[none, X], [s, H]]];
nVPValidBitA ← SIBISS[TRUE, nVPValidBitA, [[none, X], [s, H]]];
RPValidBitA ← SIBISS[TRUE, RPValidBitA, [[none, X], [s, H]]];
nRPValidBitA ← SIBISS[TRUE, nRPValidBitA, [[none, X], [s, H]]];
RPDirtyBitA ← SIBISS[TRUE, RPDirtyBitA, [[none, X], [s, H]]];
nRPDirtyBitA ← SIBISS[TRUE, nRPDirtyBitA, [[none, X], [s, H]]];
QValidA ← SIBISS[TRUE, QValidA, [[none, X], [s, H]]];
nQValidA ← SIBISS[TRUE, nQValidA, [[none, X], [s, H]]];
QMasterA ← SIBISS[TRUE, QMasterA, [[none, X], [s, H]]];
nQMasterA ← SIBISS[TRUE, nQMasterA, [[none, X], [s, H]]];
QSharedA ← SIBISS[TRUE, QSharedA, [[none, X], [s, H]]];
nQSharedA ← SIBISS[TRUE, nQSharedA, [[none, X], [s, H]]];
};
The next block of code assumes that the instructions have been set to none and only sets the instructions if a strength other than none is to be applied.
Assert[NOT MoreThanOneOf[SetSharedA, ResetVPValidA, SetFlagsA, ResetMasterA]];
IF Resetb AND PhAb THEN {
[VPValidBitA, nVPValidBitA] ← DriveBit[VPValidBitA, nVPValidBitA, FALSE];
[RPValidBitA, nRPValidBitA] ← DriveBit[RPValidBitA, nRPValidBitA, FALSE];
[RPDirtyBitA, nRPDirtyBitA] ← DriveBit[RPDirtyBitA, nRPDirtyBitA, FALSE];
[QMasterA, nQMasterA] ← DriveBit[QMasterA, nQMasterA, FALSE];
[QSharedA, nQSharedA] ← DriveBit[QSharedA, nQSharedA, FALSE];
[QValidA, nQValidA] ← DriveBit[QValidA, nQValidA, FALSE];
};
IF SetSharedA THEN [QSharedA, nQSharedA] ← DriveBit[QSharedA, nQSharedA, TRUE];
IF SetRPDirtyVPValidA THEN {
[VPValidBitA, nVPValidBitA] ← DriveBit[VPValidBitA, nVPValidBitA, LatchVPValidBA];
[RPDirtyBitA, nRPDirtyBitA] ← DriveBit[RPDirtyBitA, nRPDirtyBitA, LatchRPDirtyBA];
};
IF FlagLatchB THEN {
LatchVPValidBA ← EBFD[MDataI, 32, 30];
LatchRPDirtyBA ← EBFD[MDataI, 32, 31];
};
IF ResetVPValidA THEN [VPValidBitA, nVPValidBitA] ← DriveBit[VPValidBitA, nVPValidBitA, FALSE];
IF SetFlagsA THEN {
[VPValidBitA, nVPValidBitA] ← DriveBit[VPValidBitA, nVPValidBitA, TRUE];
[RPValidBitA, nRPValidBitA] ← DriveBit[RPValidBitA, nRPValidBitA, TRUE];
[RPDirtyBitA, nRPDirtyBitA] ← DriveBit[RPDirtyBitA, nRPDirtyBitA, NOT IsCleanBA];
[QMasterA, nQMasterA] ← DriveBit[QMasterA, nQMasterA, FALSE];
[QSharedA, nQSharedA] ← DriveBit[QSharedA, nQSharedA, LatchSharedBA];
[QValidA, nQValidA] ← DriveBit[QValidA, nQValidA, TRUE];
};
IF ResetMasterA THEN [QMasterA, nQMasterA] ← DriveBit[QMasterA, nQMasterA, FALSE];
IF PhAb THEN {
RefreshCountAB ← RefreshCountBA;
VictimCountAB ← VictimCountBA;
VictimDirtyBitsAB ← VictimDirtyBitsBA;
};
IF IncrementRefreshB THEN RefreshCountBA ← (RefreshCountAB+1) MOD 512;
IF IncrementVictimB THEN VictimCountBA ← (VictimCountAB+1) MOD 4;
Assert[NOT MoreThanOneOf[SampleDirtyBitsB, DeleteDirtyBitB]];
IF SampleDirtyBitsB THEN VictimDirtyBitsBA ← nQDirtyB;
FOR i:[0..4) IN [0..4) DO
IF EBFW[VictimDirtyBitsAB, 4, i] THEN {
SomeDirtyBA ← TRUE;
EXIT;
};
EXITS
FINISHED => SomeDirtyBA ← FALSE;
ENDLOOP;
IF DeleteDirtyBitB THEN FOR i:[0..4) IN [0..4) DO
IF EBFW[VictimDirtyBitsAB, 4, i] THEN {
VictimDirtyBitsBA ← IBIW[FALSE, VictimDirtyBitsAB, 4, i];
EXIT;
};
ENDLOOP;
DoGetAdrBA ← MGntSenseBA AND IfGrantThenGetAdrElseRefreshToDecoderBA;
DoRefreshBA ← ((NOT MGntSenseBA) AND IfGrantThenGetAdrElseRefreshToDecoderBA) OR RefreshToDecoderBA;
Assert[NOT MoreThanOneOf[VictimToDecoderBA, DoRefreshBA]];
IF VictimToDecoderBA THEN CellAdrBA ← MWTW[VictimCountBA, 7, 0, 7, 0, 7, 0, 7];
Assert[NOT MoreThanOneOf[DoRefreshBA, DirtyBitsToMQSelBA, Adr2829ToMQSelBA]];
IF DoRefreshBA THEN {
CellAdrBA ← MWTW[RefreshCountBA, 9, 0, 7, 0, 7, 0, 7];
MQSelBA ← SELECT ECFW[RefreshCountBA, 9, 7, 2] FROM
0 => 1,
1 => 2,
2 => 4,
3 => 8,
ENDCASE => ERROR;
};
nCellAdrBA ← WNOT[CellAdrBA, 7];
IF Resetb THEN MQSelBA ← 0FH;
IF DirtyBitsToMQSelBA THEN {
MQSelBA ← 0;
FOR i:[0..4) IN [0..4) DO
IF EBFW[VictimDirtyBitsBA, 4, i] THEN {
MQSelBA ← IBIW[TRUE, 0, 4, i];
EXIT;
};
ENDLOOP;
};
Assert[NOT MoreThanOneOf[SamplePAdr2829B, SampleMAdr2829B]];
IF SamplePAdr2829B THEN Adr2829BA ← ECFW[PAdr2829AB, 4, 0, 2];
IF SampleMAdr2829B THEN Adr2829BA ← ECFD[MDataI, 32, 28, 2];
IF Adr2829ToMQSelBA THEN MQSelBA ← SELECT Adr2829BA FROM
0 => 1,
1 => 2,
2 => 4,
3 => 8,
ENDCASE => ERROR;
Assert[NOT MoreThanOneOf[AddressBitsToMDataIA, AddressBitsLowZeroToMDataIA]];
IF AddressBitsToMDataIA THEN MDataI ← MWTD[PAdr2829AB, 4, 0, 4, MDataI, 32, 28, 4];
IF AddressBitsLowZeroToMDataIA THEN {
MDataI ← MWTD[PAdr2829AB, 4, 0, 2, MDataI, 32, 28, 2];
MDataI ← ICID[0, MDataI, 32, 30, 2];
};
SelMapAdrBA ← DoGetAdrBA AND GetAdrCmdBA=RefRealAssemble;
SelRPBA ← (DoGetAdrBA AND GetAdrCmdBA=VictimReal) OR SelectRPBA;
SelRealDataBA ← DoRefreshBA OR SelectRealDataBA;
IF PhBb THEN ForceAllDataSelectsBA ← Resetb;
ENDCELL