<> <> Directory Dragon; Library CacheMCtlSequencer, CacheMCtlEntryCtl, CacheMCtlFlagCtl, CacheMCtlRAMCtl, CacheMCtlCAMCtl; MCtl: CELL[ <> Vdd, Gnd> <> PhAb, PhBb> nVirtualMatch, nMatchPageClean, nMatchCellShared=BOOL, nMapValid, nRealMatch, nVictimClean=BOOL, CellAdr, nCellAdr>INT[8], VirtualAccess, nVirtualAccess, SelCell, SelVictimAdr, SelMapAdr, SelRealData, SelPageFlag, SelVictimData, SelRealAdr>BOOL, FinishSharedStore>BOOL, VPValid, nVPValid, RPValid, nRPValid, RPDirty, nRPDirty, Master, nMaster, Shared, nShared, Victim, nVictim, TIP, nTIP, Broken, nBroken=BIT, MAdrLow, nMAdrLow>BOOL, VictimFeedback, nVictimFeedback, ShiftVictim, nShiftVictim>BOOL, ForceDataSelect>BOOL, <

M control>> MDoneAB, MHeldAB>BOOL, MFaultAB>EnumType["Dragon.PBusFaults"], PAdrHigh, PAdrLowToM> DoShiftBA, DoExecuteBA, DoHoldBA> <> MDataI=INT[32], MDataDrive, MDataIDrive, MDataPipeBypass, MDataPipeTransfer>BOOL, MCmdInEnumType["Dragon.MBusCommands"], MCmdDrive>BOOL, MCmdDriveToDataTransport>BOOL, MCmdDriveToNoOp>BOOL, MNSharedSenseBABOOL, MNSharedDriveLow>BOOL, MNErrorDriveLow>BOOL, MReadySenseBOOL, MNewRqIBA>BOOL, MNewRqEnableBA>BOOL, MGntSense> ShiftDataToMCtlBOOL, ShiftEqual, nShiftEqual, ShiftFeedBack, nShiftFeedBack, ShiftShift, nShiftShift>BOOL, <<>> <> PageAccessToAccess, BlockAccessToAccess>BOOL, PageVirtualToAccess, BlockVirtualToAccess>BOOL, MatchToAccess>BOOL, MDataToMatch, AccessToMatch>BOOL, PageAccessToMData, nPageAccessToMData>BOOL, BlockAccessToMData, nBlockAccessToMData>BOOL, AccessToPageBlockAccess, nAccessToPageBlockAccess, ShiftToPageBlockAccess, nShiftToPageBlockAccess, AccessDrive, nAccessDrive>BOOL, PageBlockAccessToShift, nPageBlockAccessToShift>BOOL, nCAMAccessPrecharge>BOOL, <> nMBitsPrecharge, MuxRight, MuxLeft, MBitsDrive, nMBitsDrive, MRamRegToMDataI, nMRamRegToMDataI, SenseMBits, SenseMDataI, ParityIn>BOOL, ParityOutBOOL, MRamRegToMBits, nMRamRegToMBits>BOOL, ShiftToMBits, nShiftToMBits, MBitsToShift, nMBitsToShift>BOOL ] Expand <> ShiftDataToFlagCtl, ShiftDataToSequencer, ShiftDataToEntryCtl, ShiftDataToCAMCtl: BOOL; ShiftExecute, nShiftExecute: BOOL; ReadEntry, WriteEntry: BOOL; <> CAMMDataIToMatchReg, CAMGetAdrRefresh, CAMGetAddress, CAMPageAccessToMDataI, CAMLowBitsAccessToMDataI, CAMAccessToMatch, CAMMatchToAccess, CAMVirtualAddressToAccess, CAMDriveCAMAccess: BOOL; <<>> <> RAMMDataIToMRAMReg, RAMMBitsToMRAMReg, RAMMRAMRegToMDataI, RAMMRAMRegToMBits, RAMMRAMRegToMBitsNoOrphan, RAMPBitsToMRAMReg, RAMLeftPBitsToMRAMReg, RAMMRAMRegToPBits: BOOL; <> FlagSetShared, FlagRPDirtyVPValid, FlagFlagLatch, FlagResetVPValid, FlagSetFlags, FlagSetTIP, FlagResetTIP, FlagResetMaster: BOOL; <<>> <> EntryMDataIToMAdrCtr, EntryGetAddress, EntryGetAdrRefresh, EntryRefresh, EntryMAdrCtrToMAdr, EntryIncMAdrCtr, EntryZeroMAdrCtr, EntryPAdrToMAdrCtr, EntryLowBitsAccessToMDataI, EntryLowBitsZeroToMDataI, EntrySelRealData, EntrySelPageFlag, EntrySelVictimData, EntrySelectVictimOrOrphan, EntryVirtualAccess, EntrynVirtualAccess, EntryShiftVictim, EntryFinishSharedStore: BOOL; <> GetAdrCmdBA: Mnemonic["GetAddressCommands"]; GetAddressDoneBA: BOOL; LatchSharedAB: BOOL; IsNoOpBA, IsCleanBA, MatchRealBA: BOOL; MAdrHigh: BOOL; mCtlSequencer:MCtlSequencer[]; mCtlEntryCtl:MCtlEntryCtl[]; mCtlFlagCtl:MCtlFlagCtl[]; mCtlRAMCtl:MCtlRAMCtl[]; mCtlCAMCtl:MCtlCAMCtl[] ENDCELL