DIRECTORY BitOps, Core, CoreCreate, Ports, Rosemary, RosemaryUser; MCImpl: CEDAR PROGRAM IMPORTS CoreCreate, Ports, Rosemary, RosemaryUser ~ BEGIN Clock, ResetIn, ResetOut, ErrorIn, ErrorOut, HdrCycle, DataCycle, DataIn, SharedIn, OwnerIn, Rqst, Gnt, DataOut, SharedOut, OwnerOut, RAS, CAS, WE, RamAddress, RamData, Check, Vdd, Gnd: NAT; ROPE: TYPE = Core.ROPE; Port: TYPE = Ports.Port; Block: TYPE = BitOps.BitQWord; Queue: TYPE = REF QueueRec; QueueRec: TYPE = RECORD[head, tail: CARDINAL, data: SEQUENCE size: NAT OF Block]; Push: PROC [q: Queue, data: Block] ~ { q.data[q.head] _ data; IF q.head= q.size THEN q.head _ 0 ELSE q.head _ q.head+1; IF q.head=q.tail THEN ERROR; --overflow }; Pop: PROC [q: Queue] RETURNS [data: Block] ~ { IF q.head=q.tail THEN ERROR; --underflow data _ q.data[q.tail]; IF q.tail= q.size THEN q.tail _ 0 ELSE q.tail _ q.tail+1; }; OutputReady: PROC [q: Queue] RETURNS [BOOL] ~ { RETURN[q.head#q.tail]; }; Handle: TYPE = REF HandleRec; HandleRec: TYPE = RECORD [ inputQueue: Queue, outputQueue: Queue ]; InitPortIndicies: PROC [ct: Core.CellType] ~ { Clock _ Ports.PortIndex[ct.public, "Clock"]; ResetIn _ Ports.PortIndex[ct.public, "ResetIn"]; ResetOut _ Ports.PortIndex[ct.public, "ResetOut"]; ErrorIn _ Ports.PortIndex[ct.public, "ErrorIn"]; ErrorOut _ Ports.PortIndex[ct.public, "ErrorOut"]; HdrCycle _ Ports.PortIndex[ct.public, "HdrCycle"]; DataCycle _ Ports.PortIndex[ct.public, "DataCycle"]; DataIn _ Ports.PortIndex[ct.public, "DataIn"]; SharedIn _ Ports.PortIndex[ct.public, "SharedIn"]; OwnerIn _ Ports.PortIndex[ct.public, "OwnerIn"]; Rqst _ Ports.PortIndex[ct.public, "Rqst"]; Gnt _ Ports.PortIndex[ct.public, "Gnt"]; DataOut _ Ports.PortIndex[ct.public, "DataOut"]; SharedOut _ Ports.PortIndex[ct.public, "SharedOut"]; OwnerOut _ Ports.PortIndex[ct.public, "OwnerOut"]; RAS _ Ports.PortIndex[ct.public, "RAS"]; CAS _ Ports.PortIndex[ct.public, "CAS"]; WE _ Ports.PortIndex[ct.public, "WE"]; RamAddress _ Ports.PortIndex[ct.public, "RamAddress"]; RamData _ Ports.PortIndex[ct.public, "RamData"]; Check _ Ports.PortIndex[ct.public, "Check"]; Vdd _ Ports.PortIndex[ct.public, "Vdd"]; Gnd _ Ports.PortIndex[ct.public, "Gnd"]; }; Init: PROC [ct: Core.CellType] = { sim: Rosemary.Simulation; InitPortIndicies[ct]; [] _ Ports.InitTesterDrive[wire: ct.public[Clock], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[ResetIn], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[ResetOut], initDrive: none]; [] _ Ports.InitTesterDrive[wire: ct.public[ErrorIn], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[ErrorOut], initDrive: none]; [] _ Ports.InitTesterDrive[wire: ct.public[HdrCycle], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[DataCycle], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[DataIn], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[SharedIn], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[OwnerIn], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[Rqst], initDrive: none]; [] _ Ports.InitTesterDrive[wire: ct.public[Gnt], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[DataOut], initDrive: none]; [] _ Ports.InitTesterDrive[wire: ct.public[SharedOut], initDrive: none]; [] _ Ports.InitTesterDrive[wire: ct.public[OwnerOut], initDrive: none]; [] _ Ports.InitTesterDrive[wire: ct.public[RAS], initDrive: none]; [] _ Ports.InitTesterDrive[wire: ct.public[CAS], initDrive: none]; [] _ Ports.InitTesterDrive[wire: ct.public[WE], initDrive: none]; [] _ Ports.InitTesterDrive[wire: ct.public[RamAddress], initDrive: none]; [] _ Ports.InitTesterDrive[wire: ct.public[RamData], initDrive: none]; [] _ Ports.InitTesterDrive[wire: ct.public[Check], initDrive: none]; [] _ Rosemary.SetFixedWire[ct.public[Vdd], H]; [] _ Rosemary.SetFixedWire[ct.public[Gnd], L]; sim _ RosemaryUser.TestProcedureViewer[name: "Memory Controller Tester", cellType: ct, testButtons: LIST["TestMC"], displayWires: RosemaryUser.DisplayCellTypePortLeafWires[ct], flatten: FALSE]; }; TestMC: RosemaryUser.TestProc = { InitPortIndicies[cellType]; }; memoryName: ROPE = Rosemary.Register[roseClassName: "MemoryController", init: MCInit, evalSimple: MCSimple]; MemoryController: PROC RETURNS [ct: Core.CellType] = { ct _ CoreCreate.Cell[ public: CoreCreate.WireList[LIST[ "Clock", "ResetIn", "ResetOut", "ErrorIn", "ErrorOut", --controlPort "HdrCycle", "DataCycle", CoreCreate.Seq["DataIn", 64], "SharedIn", "OwnerIn", --receivePort CoreCreate.Seq["Rqst", 5], "Gnt", CoreCreate.Seq["DataOut", 64], "SharedOut", "OwnerOut", --sendPort "RAS", "CAS", "WE", CoreCreate.Seq["RamAddress", 5], CoreCreate.Seq["RamData", 64], CoreCreate.Seq["Check", 8], --ramInterface "Vdd", "Gnd" --power ], "MCInterface", NIL], name: memoryName, instances: NIL ]; [] _ Ports.InitPort[wire: ct.public[0], levelType: b]; --controlPort [] _ Ports.InitPort[wire: ct.public[1], levelType: b]; [] _ Ports.InitPort[wire: ct.public[2], levelType: b]; [] _ Ports.InitPort[wire: ct.public[3], levelType: b]; [] _ Ports.InitPort[wire: ct.public[4], levelType: b]; [] _ Ports.InitPort[wire: ct.public[5], levelType: b]; --receivePort [] _ Ports.InitPort[wire: ct.public[6], levelType: b]; [] _ Ports.InitPort[wire: ct.public[7], levelType: q]; [] _ Ports.InitPort[wire: ct.public[8], levelType: b]; [] _ Ports.InitPort[wire: ct.public[9], levelType: b]; [] _ Ports.InitPort[wire: ct.public[10], levelType: c]; --sendPort [] _ Ports.InitPort[wire: ct.public[11], levelType: b]; [] _ Ports.InitPort[wire: ct.public[12], levelType: q]; [] _ Ports.InitPort[wire: ct.public[13], levelType: b]; [] _ Ports.InitPort[wire: ct.public[14], levelType: b]; [] _ Ports.InitPort[wire: ct.public[15], levelType: b]; --ramInterface [] _ Ports.InitPort[wire: ct.public[16], levelType: b]; [] _ Ports.InitPort[wire: ct.public[17], levelType: b]; [] _ Ports.InitPort[wire: ct.public[18], levelType: c]; [] _ Ports.InitPort[wire: ct.public[19], levelType: q]; [] _ Ports.InitPort[wire: ct.public[20], levelType: c]; [] _ Ports.InitPort[wire: ct.public[21], levelType: b]; --power [] _ Ports.InitPort[wire: ct.public[22], levelType: b]; }; MCInit: Rosemary.InitProc = { h: Handle _ NEW[HandleRec]; h.inputQueue _ NEW[QueueRec[16]]; h.outputQueue _ NEW[QueueRec[16]]; stateAny _ h }; MCSimple: Rosemary.EvalProc = { h: Handle _ NARROW[stateAny]; ServiceDynaBusInput[p, h]; }; ServiceDynaBusInput: PROC [p: Port, h: Handle] ~ { }; RosemaryUser.RegisterTestProc["TestMC", TestMC]; END. .MCImpl.mesa Copyright c 1986 by Xerox Corporation. All rights reserved. Gasbarro August 5, 1986 1:52:53 pm PDT Last Edited by: Gasbarro August 8, 1986 4:49:22 pm PDT --PROC [cellType: Core.CellType, p: Ports.Port] RETURNS [stateAny: REF ANY _ NIL]-- --PROC [p: Ports.Port, stateAny: REF ANY]-- ÊI˜code™Kšœ Ïmœ1™