MCImpl.mesa
Copyright © 1986 by Xerox Corporation. All rights reserved.
Gasbarro August 5, 1986 1:52:53 pm PDT
Last Edited by: Gasbarro August 8, 1986 4:49:22 pm PDT
DIRECTORY
BitOps, Core, CoreCreate, Ports, Rosemary, RosemaryUser;
MCImpl: CEDAR PROGRAM
IMPORTS CoreCreate, Ports, Rosemary, RosemaryUser
~ BEGIN
Clock, ResetIn, ResetOut, ErrorIn, ErrorOut, HdrCycle, DataCycle, DataIn, SharedIn, OwnerIn, Rqst, Gnt, DataOut, SharedOut, OwnerOut, RAS, CAS, WE, RamAddress, RamData, Check, Vdd, Gnd: NAT;
ROPE: TYPE = Core.ROPE;
Port: TYPE = Ports.Port;
Block: TYPE = BitOps.BitQWord;
Queue: TYPE = REF QueueRec;
QueueRec: TYPE = RECORD[head, tail: CARDINAL, data: SEQUENCE size: NAT OF Block];
Push:
PROC [q: Queue, data: Block] ~ {
q.data[q.head] ← data;
IF q.head= q.size THEN q.head ← 0 ELSE q.head ← q.head+1;
IF q.head=q.tail THEN ERROR; --overflow
};
Pop:
PROC [q: Queue]
RETURNS [data: Block] ~ {
IF q.head=q.tail THEN ERROR; --underflow
data ← q.data[q.tail];
IF q.tail= q.size THEN q.tail ← 0 ELSE q.tail ← q.tail+1;
};
OutputReady:
PROC [q: Queue]
RETURNS [
BOOL] ~ {
RETURN[q.head#q.tail];
};
Handle: TYPE = REF HandleRec;
HandleRec:
TYPE =
RECORD [
inputQueue: Queue,
outputQueue: Queue
];
InitPortIndicies:
PROC [ct: Core.CellType] ~ {
Clock ← Ports.PortIndex[ct.public, "Clock"];
ResetIn ← Ports.PortIndex[ct.public, "ResetIn"];
ResetOut ← Ports.PortIndex[ct.public, "ResetOut"];
ErrorIn ← Ports.PortIndex[ct.public, "ErrorIn"];
ErrorOut ← Ports.PortIndex[ct.public, "ErrorOut"];
HdrCycle ← Ports.PortIndex[ct.public, "HdrCycle"];
DataCycle ← Ports.PortIndex[ct.public, "DataCycle"];
DataIn ← Ports.PortIndex[ct.public, "DataIn"];
SharedIn ← Ports.PortIndex[ct.public, "SharedIn"];
OwnerIn ← Ports.PortIndex[ct.public, "OwnerIn"];
Rqst ← Ports.PortIndex[ct.public, "Rqst"];
Gnt ← Ports.PortIndex[ct.public, "Gnt"];
DataOut ← Ports.PortIndex[ct.public, "DataOut"];
SharedOut ← Ports.PortIndex[ct.public, "SharedOut"];
OwnerOut ← Ports.PortIndex[ct.public, "OwnerOut"];
RAS ← Ports.PortIndex[ct.public, "RAS"];
CAS ← Ports.PortIndex[ct.public, "CAS"];
WE ← Ports.PortIndex[ct.public, "WE"];
RamAddress ← Ports.PortIndex[ct.public, "RamAddress"];
RamData ← Ports.PortIndex[ct.public, "RamData"];
Check ← Ports.PortIndex[ct.public, "Check"];
Vdd ← Ports.PortIndex[ct.public, "Vdd"];
Gnd ← Ports.PortIndex[ct.public, "Gnd"];
};
Init:
PROC [ct: Core.CellType] = {
sim: Rosemary.Simulation;
InitPortIndicies[ct];
[] ← Ports.InitTesterDrive[wire: ct.public[Clock], initDrive: force];
[] ← Ports.InitTesterDrive[wire: ct.public[ResetIn], initDrive: force];
[] ← Ports.InitTesterDrive[wire: ct.public[ResetOut], initDrive: none];
[] ← Ports.InitTesterDrive[wire: ct.public[ErrorIn], initDrive: force];
[] ← Ports.InitTesterDrive[wire: ct.public[ErrorOut], initDrive: none];
[] ← Ports.InitTesterDrive[wire: ct.public[HdrCycle], initDrive: force];
[] ← Ports.InitTesterDrive[wire: ct.public[DataCycle], initDrive: force];
[] ← Ports.InitTesterDrive[wire: ct.public[DataIn], initDrive: force];
[] ← Ports.InitTesterDrive[wire: ct.public[SharedIn], initDrive: force];
[] ← Ports.InitTesterDrive[wire: ct.public[OwnerIn], initDrive: force];
[] ← Ports.InitTesterDrive[wire: ct.public[Rqst], initDrive: none];
[] ← Ports.InitTesterDrive[wire: ct.public[Gnt], initDrive: force];
[] ← Ports.InitTesterDrive[wire: ct.public[DataOut], initDrive: none];
[] ← Ports.InitTesterDrive[wire: ct.public[SharedOut], initDrive: none];
[] ← Ports.InitTesterDrive[wire: ct.public[OwnerOut], initDrive: none];
[] ← Ports.InitTesterDrive[wire: ct.public[RAS], initDrive: none];
[] ← Ports.InitTesterDrive[wire: ct.public[CAS], initDrive: none];
[] ← Ports.InitTesterDrive[wire: ct.public[WE], initDrive: none];
[] ← Ports.InitTesterDrive[wire: ct.public[RamAddress], initDrive: none];
[] ← Ports.InitTesterDrive[wire: ct.public[RamData], initDrive: none];
[] ← Ports.InitTesterDrive[wire: ct.public[Check], initDrive: none];
[] ← Rosemary.SetFixedWire[ct.public[Vdd], H];
[] ← Rosemary.SetFixedWire[ct.public[Gnd], L];
sim ← RosemaryUser.TestProcedureViewer[name: "Memory Controller Tester", cellType: ct, testButtons: LIST["TestMC"], displayWires: RosemaryUser.DisplayCellTypePortLeafWires[ct], flatten: FALSE];
};
TestMC: RosemaryUser.TestProc = {
InitPortIndicies[cellType];
};
memoryName:
ROPE = Rosemary.Register[roseClassName: "MemoryController", init: MCInit, evalSimple: MCSimple];
MemoryController:
PROC
RETURNS [ct: Core.CellType] = {
ct ← CoreCreate.Cell[
public: CoreCreate.WireList[
LIST[
"Clock", "ResetIn", "ResetOut", "ErrorIn", "ErrorOut", --controlPort
"HdrCycle", "DataCycle", CoreCreate.Seq["DataIn", 64], "SharedIn", "OwnerIn", --receivePort
CoreCreate.Seq["Rqst", 5], "Gnt", CoreCreate.Seq["DataOut", 64], "SharedOut", "OwnerOut", --sendPort
"RAS", "CAS", "WE", CoreCreate.Seq["RamAddress", 5], CoreCreate.Seq["RamData", 64], CoreCreate.Seq["Check", 8], --ramInterface
"Vdd", "Gnd" --power
], "MCInterface", NIL],
name: memoryName,
instances: NIL
];
[] ← Ports.InitPort[wire: ct.public[0], levelType: b]; --controlPort
[] ← Ports.InitPort[wire: ct.public[1], levelType: b];
[] ← Ports.InitPort[wire: ct.public[2], levelType: b];
[] ← Ports.InitPort[wire: ct.public[3], levelType: b];
[] ← Ports.InitPort[wire: ct.public[4], levelType: b];
[] ← Ports.InitPort[wire: ct.public[5], levelType: b]; --receivePort
[] ← Ports.InitPort[wire: ct.public[6], levelType: b];
[] ← Ports.InitPort[wire: ct.public[7], levelType: q];
[] ← Ports.InitPort[wire: ct.public[8], levelType: b];
[] ← Ports.InitPort[wire: ct.public[9], levelType: b];
[] ← Ports.InitPort[wire: ct.public[10], levelType: c]; --sendPort
[] ← Ports.InitPort[wire: ct.public[11], levelType: b];
[] ← Ports.InitPort[wire: ct.public[12], levelType: q];
[] ← Ports.InitPort[wire: ct.public[13], levelType: b];
[] ← Ports.InitPort[wire: ct.public[14], levelType: b];
[] ← Ports.InitPort[wire: ct.public[15], levelType: b]; --ramInterface
[] ← Ports.InitPort[wire: ct.public[16], levelType: b];
[] ← Ports.InitPort[wire: ct.public[17], levelType: b];
[] ← Ports.InitPort[wire: ct.public[18], levelType: c];
[] ← Ports.InitPort[wire: ct.public[19], levelType: q];
[] ← Ports.InitPort[wire: ct.public[20], levelType: c];
[] ← Ports.InitPort[wire: ct.public[21], levelType: b]; --power
[] ← Ports.InitPort[wire: ct.public[22], levelType: b];
};
MCInit: Rosemary.InitProc = {
--PROC [cellType: Core.CellType, p: Ports.Port] RETURNS [stateAny: REF ANY ← NIL]--
h: Handle ← NEW[HandleRec];
h.inputQueue ← NEW[QueueRec[16]];
h.outputQueue ← NEW[QueueRec[16]];
stateAny ← h
};
MCSimple: Rosemary.EvalProc = {
--PROC [p: Ports.Port, stateAny: REF ANY]--
h: Handle ← NARROW[stateAny];
ServiceDynaBusInput[p, h];
};
ServiceDynaBusInput:
PROC [p: Port, h: Handle] ~ {
};
RosemaryUser.RegisterTestProc["TestMC", TestMC];
END.