///MBusSpecs.tiogaWrittenby:Sindhu,September1,19841:51:14pmPDTLastEditedby:Sindhu,September10,19846:47:15pmPDTLastEditedby:Barth,December13,19842:08:47pmPSTTheDragonMBusDescriptionandSpecificationsReleaseas[Indigo]Documentation>MBus>MBusSpecs.tioga,.presscCopyright1984XeroxCorporation.Allrightsreserved.Abstract:ThismemodescribestheDragonMbus.ItisintendedtobeusedbothasaconvenientsourceforinformationabouttheMbusandasareferencemanualforbusspecifications.ThememobeginswithabriefoverviewoftheMbus.Itthenlistsallthebussignalsanddefinesthemeaningofeachsignalgroup.Next,itusesthesesignalstodescribeindetailhowthebusoperatesatboththecycleandtransactionlevels,andhowcertaintransactionsareusedtomaintaincacheconsistency.Finally,itgivesthedetailedtimingofthebustransactionscurrentlydefined.XEROXXeroxCorporationPaloAltoResearchCenter3333CoyoteHillRoadPaloAlto,California94304ForInternalXeroxUseOnlyp_:]<@!#j&+-[E$9&v).0ZDE#%T(-/qQ" rM  D sHeHtHHg1>'" !J#k +/1z358z:N;r<`891RF")+*-/224S7:<?F7 q#%R'=+/5 9:x>5(3w"&6),&2488; ?04; Wc!& /E157=2 #&,1369 0wt.2 5.25&;.2Y7c9.25 <6r I"=&TVm$DRAGONMBUSSPECIFICATIONS2Contents1.Introduction2.BusSignals3.BusOperation4.BusTimingA.IOAddressSpaceDefinitionDRAGONPROJECTFORINTERNALXEROXUSEONLYxg y!$gg!x%gg'y(gg)x+gyg+ tgEz^{[0 XX0U 0Q0Nls y /%'.*0y47TVm$qDRAGONMBUSSPECIFICATIONS3 1.IntroductionTheMbusisahighbandwidthsynchronousbusthatconnectsthecomponentsofaDragoncluster.ADragoncluster(Figure1)consistsofoneormoreDragonprocessorsattatchedtothebusthroughcaches,somemainmemory,amapprocessor,adisplaycontroller,andoneormoreI/Oprocessors.Thereareapproximately75wiresontheMbus.Themultiplexeddata/addresspath,whichischeckedbyasingleparitybit,is32bitswide.Fouradditionalwiresdefinethebuscommand,whichencodestheactionduringthecurrentbuscycle(abuscycleisdefinedinthesamewayasaprocessorcycle:namely,onecompleteperiodofthesystem-widetwo-phaseclock;thesetwophasesarelabeledAandB,byconvention).Apairofrequest/grantlinesforeachbusrequestoralongwithmiscellaneouscontrollinesmakeuptheremainingsignalsonthebus.AddressesontheMbusarerealasopposedtovirtual,andtheunitofaddressingisthe32bitword.However,forefficientbusutilizationthetransfertoandfrommemoryisin4-wordchunkscalledquads.Thereisasingle,centralarbiterthatpermitstheMbustobetimemultiplexedbetweentwoormorecontendingdevices.Thesedevicesmakerequeststothearbiterusingthededicatedrequestlines,andthearbitergrantsthebususingthededicatedgrantlines.Thearbiterusesaround-robinalgorithmtoguaranteefair(bounded-time)servicetoeachrequestor.Adevicethathasbeengrantedthebusiscalledbusmaster.Thesequenceofcyclesinitiatedbyamasterwilltypicallyinvolveatleastoneotherdeviceonthebus;suchadeviceiscalledaslave.Currently,theonlydevicesthatcanbecomemasterarethecaches.Cachescanalsoactasslaves,ascanalloftheotherdevices.SomeMbuscommandsstartafixedsequenceofcyclesthatarereferredtoastransactions.Transactionsprovidethemechanismforusingthe32-bitwidedatapathfortransferringmulti-worditemssuchasquads,andalsopermitthetransferofdataonthebustobeflowcontrolled.Fivetransactionsarecurrentlydefined:ReadQuad,WriteQuad,WriteSingle,IORead,andIOWrite.ReadQuadpermitsacachetoreadaquadfromanothercacheorfrommainmemory.WriteQuadisthelogicalinverseofReadQuad.WriteSingleistheoperationusedbyacachetowriteasinglewordtoanothercache.IOReadandIOWritearegeneralizedIOoperationsthatareusedtodomapoperationsaswellastotransferdatatoandfromIOdevices.Theremainderofthedocumentgoesintogreaterdetailaboutthestructure,operation,andtimingoftheMbus.Thenextsectionliststhebussignalsindetailandgivesthemeaningofeachsignal.Section3nextusesthesesignaldefinitionstoexplainhowthebusoperates:itdiscussesarbitration,liststhesetofbuscommandscurrentlydefined,showshowthesecommandsareusedineachofthepossibletransactions,andhowtransactionsareusedtomaintaincacheconsistency.Finally,Section4discussesthetimingofarbitrationandofeachtransactionindetail.Theappendicesprovidedetailsthatdonoteasilyfitintothemaindocument.2.BusSignalsTheMbushas73signallinesthatarelistedbelow,togetherwiththemeaningofeachgroupoflines.Thedescriptionusesthefollowingnamingconventions:S[a..b)denotesagroupofb-alinesthatencodethebitsrepresentingthesignalS;DRAGONPROJECTFORINTERNALXEROXUSEONLYxg y!$gg!x%gg'y(gg)x+gyg+ tgEz^ x[tF8Zx%L -2/28:r YL"'i,`.3*479}=XX ^+!|&+$.178; V  V  "}&( T5 "&I(G*,p/2 p:/T5T5:xP'p4PPxPP"(*z.35:Z<@{O?- +#&()049i<6MK O%)-0M47#;=@ZK {~p bKK x$}KpK%.xK(,V.24;?JI pJIJI#xJI="$':-246X9@HYKe3"$P)+.a1]3- : ;>@FP!(# *?,13f6"9>@pESHp?ESESxESESB,j %X(!-/k1A35{7g: A1; #(~,j1p4A1A15@xA19;c=?#o&!({p,??-x?03X59;='*!L$& /F678?<; W"Q )[*/F2!48 =?:zpa::wx:&',135%9<8 "2$&S)@,O-V1x26p7888"x:k88; 7EiB$)+.38o;!>@p5%_Og!3"~\ #%$(.0P4L79w>@pp1{ x1{1{ $'g.1'47;?/q  #-&*4+0h356:=.,W! )~, 4K6<,<  %+.U4;@*Xpx$(J* -q070>U?)69!\ (*M,26 89+<>'a"'*t/2+ 9^;p %vw $ %(t* +03z57:<#miL&n),1|5r9< ! f{6 "s%(+0t37581<>S 1P"_'L,?-037Q;O wo!B"}#)W 0R2517,8;9"%,/248O:B<(  $&k)+c1%4 =8!#X *$,.1 8:?F O"$$&*c,2/ 1j4z< x |WdJ!5$q'@)-?17 :$< F(X?! (,.4:  7To!%7(,/N2 9<\@Yy /%'.*0y47 ETVm$tDRAGONMBUSSPECIFICATIONS4mostsignificantbitsofthesignalarewrittenleftmost.Asignalrepresentedbyasinglewireiswrittenunencumberedwiththe[)notation.Allsignalsareassumedtofollowpositivelogicunlesstheyhavean"n"atthebeginningofthesignalname.Finally,theletters"AB"areappendedtosignalSifitiscomputedduringphaseAandbecomesvalidduringthefollowingphaseB.SlavesshouldnotassumethatthebusbecomesvalidduringA.TheactualsetuptimeatwhichthebusbecomesvalidattheslavespriortothefallingedgeofBhasnotyetbeendetermined.Itisapproximately20ns.MCmdAB[0..4)ThesefourlinesencodetheMbuscommand.TheMbuscommandspecifiestheactioninprogressduringthecurrentbuscycle;itmaybeassertedeitherbythemasterorbyaslave.ThecommandscurrentlydefinedarediscussedlaterinSection3.2.MDataAB[0..32)Theinterpretationofthese32linesdependsonMCmdAB[0..4).FormostcommandstheMDataABlinessimplyrepresentthe32-bitaddressordatacorrespondingtoareadorwrite;forothercommandstheinterpretationismorecomplicated.ThedetailedinterpretationappearsinSection3.2.AswithMCmdAB,theselinesalsomaybeassertedeitherbymasterorslave.MParityABThislinecarriestheparitybitforMDataAB[0..32).Theparitycomputedisoddandisvalidonlyduringdatatransportcycles.nMSharedThislineisusedbythecachestomaintainconsistencyformultiplecopiesofread/writedata.Whenacacheputsoutareadorwriterequestonthebus,othercachesmatchtheaddressonthebuswithaddressesforwhichtheyhavevaluesstored.WheneveracachefindsamatchitpullsnMSharedlow,signalingthatthedatumisshared.Notethatthissignalisassertedwhenlow.nMAbortThislineisusedtopreventmemoryfromrespondingtoaReadQuadandhaveacacherespondinstead.LogicallyspeakingnMAbortisnotnecessary,sincenMSharedcanalsobeusedtogetthememorytoabort.However,thiswouldrequiretheimplementationtokeepanadditionalstatebitforeachcacheentry,whichisexpensive.ItwouldalsorequiremorebandwidthfromtheRAMinthecache.Notethatthissignalalsoisassertedwhenlow.nMErrorThislineisusedtosignalabuserror.Theonlybuserrorcurrentlydefinedisbusparityerror.Notethatthissignalisassertedwhenlow.Normally,apullupresistorensuresitisnotasserted.DRAGONPROJECTFORINTERNALXEROXUSEONLYxg y!$gg!x%gg'y(gg)x+gyg+ tgEx_,\  $$,&p+n_,_,+x0_,_,13J7S >@]E %(+^,3A5:(<[!$ '\)A+-o/6$7:'>Z6H_2 &(,p-/0m18C<@Xaf!(+/ 3R7:p?PVK!x#&*.13d7{9<U@LH6\!&)L+,v.1d37 ?8@S {PI xL #$'.136=<KR=Re #-'*.m/249=?I? %+m0Z28;=>H{D xAd #S%u(.0 ;>?XG z$E)E/27K<?> 'i T$r&*141 <>6(dJf!$/&*C0276:x=&#$Q()-E47<?%C2V $"&(-T1 {!xg"(+h 2}4%5H<'>h/ v&,3J57 >U!>##%(9-/4;=o "`%( .24a6:4>2 g!$)l-479=?_p [#($)-{xw"!"%),/2_5;@. #i'p(.K25KRbB &k( *04*7 <?I>!N"&)h-r34:=V{F\xC d '")+f0[267: AeP!7#(-.3>5 ;>@?md W #'.05K9Qi+ "(T /4:, #(+0,17F9=! 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QTVm$,DRAGONMBUSSPECIFICATIONS6cycleinwhichitissuesthebusbyassertingtheMGntlineforthehighestprioritydevicethathasMRqasserted.Priorityisround-robin,withthedevicelastgrantedthebusreceivinglowestpriority.ThebusrecipientkeepsMRqassertedforaslongasitwantsthebus,andthearbiterinturnkeepsMGntasserted.Ifthemasterisexecutingalongsequenceofcyclesthatisnotrequiredtobeatomicwithrespecttootherdevices,itassertsMNewRqtoindicateitswillingnesstogiveupthebusifthereareotherrequestspending(forcorrectoperation,MNewRqmustbeassertedonlybythecurrentmaster).MNewRqcausesthearbitertodoagrantcycleeventhoughthemasterstillhasMRqasserted.Sincethemasterbecamethelowestprioritydeviceuponreceivingthebus,itwilllosethebusifanyrequestsarepending.Thisstrategypreventsamasterfromhoggingthebus.Atthesametime,itavoidswastingcyclesinthecasethatnodevicesarewaitingtogetthebus.Asolutioninwhichthemasterreleasesandreacquiresthebus,forexample,doeswastecyclesinthiscase.3.2MBusCommandsThereareamaximumofsixteenMbuscommands.Nineofthesearecurrentlydefined,andtherestarereservedforfutureuse.Inthedescriptionbelow,thedecimalnumberinbracketsafterthecommandnameindicatestheencodingforthecommand.DataTransport{0}Thiscommandisusedduringcyclesinwhichdataisbeingtransportedbetweentwocachesorbetweenacacheandmainmemory.MDataAB[0..32)carriesthedata.TheMParitybussignalisvalidonlyduringDataTransportcycles.ReadQuad{1}ThiscommandisissuedbythemasterduringthefirstcycleofaReadQuadtransaction,whichreadsaquadfrommemoryorfromanothercache.Aquadisfourcontiguous32-bitwordsalignedinrealaddressspacesuchthattheaddressofthefirstwordis0MOD4.DuringthiscommandMDataAB[0..32)istheaddressofoneofthewordsinthequad,anditisthiswordthatwillbereturnedfirstduringsubsequentDataTransportcycles.WriteQuad{2}ThiscommandisissuedbythemasterduringthefirstcycleofaWriteQuadtransaction,whichwritesaquadtomemoryortoanothercache.MDataAB[0..32)holdstheaddressofthequadwhich,unliketheaddressforaReadQuadtransaction,mustbe0MOD4.WriteSingle{3}ThiscommandisusedbythemasterduringthefirstcycleofaWriteSingletransaction,whichwritesasinglewordintotherealaddressspace.WriteSingleneverwritesthewordtomemory,butonlytocachesthathavethequadcontainingthewordbeingwritten.MDataAB[0..32)carriestheaddressoftheword.DRAGONPROJECTFORINTERNALXEROXUSEONLYxg y!$gg!x%gg'y(gg)x+gyg+ tgEx_/`1}"$*?,0358`=)]*v#">'A( 036Q:=[AYd $_)+-02e37: =?WU #&;'*".0617]:z@eVi 2"$A(,H1)36<@=Tni.rd %u':*?,h.1369<R}vJ #)-k/58t:=TQ _"(&(v*+/3 6k;6=Ox3H"$)%.C05:(>Mj~!$D'(+O03G9=L*cX"$(]*T,0)3496>'JC\T w"'),=.24C9;?HR\ !$&)-p.HH/xH259;g> {ExB;^!%'X)1{469 #L%+/5W7=?=Ep9 x6Z#')l-j0_15v <4w!$Y'- 8%3Wp"g3W3W#x3W%c) 3p0x,d!8#V%*k.14{89;8+ Px0t# &,-1s6;s=@)h  %'*L/>2659 ;s@e'A yA''Rx'$p'-r 79;{@e&X!$%'h*-0{3/5(:=$r  :p!"xZ!$#=%*G.1R4H79:+ Ear#7$*p,C.37 T!%c)+023: J;yoxp fx<n e"%).@037a9B:  g 2$N(+-05: 3#&r)+3/2K57;e FA$ (c,/458y /%'.*0y47TVm$<DRAGONMBUSSPECIFICATIONS7ChangeFlags{4}ChangeFlagsisusedbytheMapprocessortogetaspecifiedsetofcachestomanipulatetheirmapentries.ThiscommandistypicallyissuedinsideanIOReadorIOWritetransaction.ThesetofcachesaddressedisencodedinMDataAB[0..4].ThevalueallonesindicatesallcachesontheMbus,andanyothervalueindicatesjustthecachesconnectedtotheprocessorwiththisvalueasitsnumber.MDataAB[5..7]isafunctioncodethatspecifiesthemanipulation,andMDataAB[8..31]containsarealpagenumber,whichisvalidonlyforsomeofthefunctioncodes.Theinterpretationofthefunctioncodesisasfollows(inthetablebelowrpstandsforrealpagenumber;vpstandsforvirtualpagenumber;wtEnabledisabitpercacheentrythatmeanswritesarepermittedtotheentry):MDataAB[5..7]MdataAB[8..31]Meaning0rpclearvpValidandwtEnabledforallvp'sthatpointtothisrp1rpsetwtEnabledforthisrp(TheundirectedversionofthiscommandisunsafebecauseitcouldcausewtEnabledtogetsetevenwhenwritesarenotpermitted:eg.twospaces,onewithwritespermitted,theothernot)2undefinedclearvpValidandwtEnabledforallvp's3undefinedclearwtEnabledforallvp'sIORead{5}IOReadisusedbyamasterduringthefirstcycleofanIOReadtransaction.MDataAB[0..31]containstheIOaddress.TheIOaddressspaceiscarvedupintodisjoint,contiguouspieces,withatmostonedevicerespondingtoeachpiece.SeeAppendixAforafulldefinition.IOWrite{6}IOWriteisusedbyamasterduringthefirstcycleofanIOWritetransaction.MDataAB[0..31]containstheIOaddress.IODone{7}IODoneisusedbyaslavedevicetoterminateanIOReadorIOWritetransactioninwhichitisparticipating.MDataAB[0..31]containstheresponseiftheinitiatingcommandwasIORead;MData[28:31]containstheM-Busfaultbits,whichareencodedasspecifiedinDragon.mesa.Reserved{8..14}DRAGONPROJECTFORINTERNALXEROXUSEONLYxg y!$gg!x%gg'y(gg)x+gyg+ tgEp_, x[ l #G&,.0238:9< @oZ5 n"%)+-26:<X1  ##$)>/168N Vi\ B"5&(*,/2{58Ni &%( ,.E25;CLNw i 8${(}*125+H } H-FZFZ#FZ-156a9DD-0!247;V=?B6B6#B6-069;=@@- 49;@>>-4E5: =?=?-/:36=;;-0,2I59D=F?99- 47:?r8H66-1 8:>4$4$#4$-156a92|2|-0!200#0-158:M<=p,x)`P#(u*-13`5r: ' !!#B)4,".T3T7 8=?F&/ ,"$s'*. 6 7;?$jC 7 p!hx4 `#(p*-1b325:: #  n "p2x3P,6!~%'2-</ 4$5;" % *0F28k9y /%'.*0y47TVm$#DRAGONMBUSSPECIFICATIONS8Commandcodes8through14arereservedforfutureuse.NoOp{15}Thiscommandisusedtoindicateidlebuscycles.3.3MBusTransactionsTherearecurrentlyfiveMbustransactions:ReadQuad,WriteQuad,WriteSingle,IORead,andIOWrite.ReadQuadReadQuadreadsaquadfrommainmemoryorfromacache,dependingonwherethecurrentvaluelies.Recallthataquadisfourcontiguous32-bitwordsalignedinrealaddressspacesuchthattheaddressofthefirstwordis0MOD4.ThenumberofcyclesinaReadQuadisvariablesincethetransactionisflowcontrolledtoallowthememorymoretimetorespondwhennecessary.InthefirstcyclethemastercacheissuesaReadQuadcommand,withMDataABequaltotheaddress.Thenfollowoneormorewaitcycles,andfinallyfourDataTransportcycles,eachcontainingoneofthefourwordsofthequad.Duringthesecycles,MCmdABandMDataABareassertedbytheslave.Notethatthefirstworddeliveredisnotnecessarilythefirstwordinthequad,butthewordactuallyrequestedbytheaddressinthefirstcycle;theotherthreewordsaredeliveredinorderofincreasingaddress(MOD4).WriteQuadWriteQuadwritesaquadtomainmemoryortoawillingcache.ThetransactionstartsoutwithaWriteQuadcommandfromthemaster,withMDataABequaltotheaddressofthequad(notethatthisaddressmustbe0MOD4,unliketheaddressforaReadQuad).ThenfollowzeroormoreNoOpcycles,withMCmdABbeingassertedbythememoryandMDataABdriventothefirstdatawordbythemaster.Whenthememoryisreadytoacceptdata,itsetsMCmdABtoDataTransport.ThisstartsasequenceoffourDataTransportcyclesinwhichthewordsaretransported.WriteSingleWriteSinglewritesasinglewordouttotherealaddressspace.UnlikeWriteQuad,aWriteSingleneversendsthewordouttomemorybutisdirectedexclusivelytocaches.WriteSinglesarenotflowcontrolled,andalwaystaketwocycles.InthefirstcyclethemasterputsoutMCmdAB_WriteSingle;MDataAB_address.InthesecondcycleitputsoutMCmdAB_DataTransport;MDataAB_datatobewritten.IOReadTheIOReadandIOWritetransactionsareusedbycachesasageneralwayofcommunicatingwiththeMapprocessorandwithIOdevices.The32bitaddressofanIOReadorIOWritedefinesalarge,unmappedIOaddressspacethatiscommontoallprocessors.Thisspaceiscarvedupintodisjoint,contiguouspieces,withatDRAGONPROJECTFORINTERNALXEROXUSEONLYxg y!$gg!x%gg'y(gg)x+gyg+ tgEx_/g3g"$&,Q.2p[xX!u&)X+{UA xQ{X!$ +2 :; PKq(pLxIr!c$(.#0 349.@HY!&L)>*.,/2 9>F]c #&)./248|9y;F]F]<.xF]>tC!p")+*0v36r =?B; i."&7)b+0[4 ;<?F@jcC!9"w)r0@3o:&=?>z# e#&*-14 ==E gt"r&y(-*.37;f;X " $w(,\/8148#>/?9 !%(&*n-29:=48O#@'M)/1N56 =4y6x6yK6x6p3Xx0 !"%+G,./38f;" .ah &e),03:l>?,xJ!$;),.jy/,,0x,24q8:?+ ]s"T#'g+/29><)kQ"7&(I*-0466<8>'?!%&m) /1m ;r>&  #')-/36S p" x~ #'*,/28%=  #'*e.)028l;(<0 N %(*- 47W=cJ !&(,&/N17:]VEYo n"q%}).03P68;>ToQ)"%:(,.k3t55:<RK-&,4uPMy  %'W,S.c02k 9>N8<Sm"&(+/v3 5:;pKVxH #o%'^)k.F24 5}8:;D F` R "*y0i8 @OD:0"')T-/F47P9>CU+ "w'*. 1$29B?AjVe #*D,.2q55 !)5 {:& x7~ %'s)W.4;8:;@p57 I&+@.r47=4/2w|"J%N'?+1n!=#%O'.X179<?r0  pF0 0 x0 p0 0 ?x0 #'+7.2345V:I=>j.e%7 b"n&)/M16HHw|?$ ,/T359=?X "$X&A+/@03h68;j>?0G ;$'*2, .:/238r9<-? RWg?!#&*5 !&*:,37a8< ?y /%'.*0y47 TVm$@DRAGONMBUSSPECIFICATIONS10onethathasn'tbeenwrittenouttomemoryyet)existsinothercachesoritdoesn't.Inthefirstcasetheowner(andpossiblyothercaches)assertnMShared.TheowneralsoassertsnMAbort,preventingthememoryfromresponding,andthenproceedstosupplythequadtothemaster.Thesecondcasebreaksdownintotwosubcases.Inthefirstsubcasenoothercachehasthequad,nMShareddoesnotgetasserted,andthequadcomesfrommemory.Inthesecondsubcaseatleastoneothercachehasthedata,thenMSharedlinedoesgetasserted,butthequadstillcomesfrommemorybecausenocacheassertednMAbort.4.BusTimingThissectiongivesthedetailedtimingofbusarbitrationandofeachofthetransactionsjustdescribed.Inthetimingdiagramsusedbelow,eachrowcorrespondstoonebuscycle.ActionsduringthecycleareindicatedusingMesalikestatements.Idlebuscyclesareindicatedbyshadingasinglerowofthetimingdiagram,witheachshadedrowrepresentingzeroormorecycles.Thevariablewwillbeusedtorepresentthenumberofwaitcycles.Foreachofthedescriptionsbelow,cycle0willbethecycleinwhichtherequestorassertsMRq.Forsimplicity,thetimingsforeachofthetransactionswillassumetheminimumarbitrationdelayofzerocycles.4.1ArbitrationThetimingforarbitrationappearsinFigure2.ArequestorassertsMRqduringphaseBofcycle0.ThearbiterlatchestherequestduringtheAofcycle1,andifthebusisfreeMGntgetsassertedintheAofcycle2.ThenewmastercandrivethebusduringtheAofcycle3.Thustheminimumarbitrationdelayisthreecycles.Ifthebusisnotfree,zeroormorewaitcyclesgetinsertedimmediatelyaftercycle1.MNewRqbehavessomewhatdifferentlythanalltheotherbuslinesasfarasmastershipisconcerned.ArequesterbecomesbusmasterwithrespecttoMNewRqduringtheBofcycle2+wwhileitacquirestherestofthebusduringtheAofcycle3+w.Conversely,itrelinquishesMNewRqduringtheBimmediatelyaftertheAduringwhichMGntfalls.TheearliestMRqcanbedeassertedisduringcycle2+w.TheearliestMGntisdeassertedinresponseisduringcycle4+w,andtheearliestanewdevicecanbecomemasterisduringcycle5+w.4.2ReadQuadFigure3showsthetimingforReadQuad.Cycles0through2aretakenupbyarbitration(recallthatweareassumingtheminimumarbitrationdelay).Thefirstcycleofthetransactioniscycle3,duringwhoseAthemastersetsMCmdAB_ReadQuad;MDataAB_RQAddress;nMShared_true;nMAbort_true.Cycle4isalwaysadeadcycle:thememorysetsMCmdAB_NoOp;slavecachessetnMSharedtofalseifthereisamatch;andaslavecachethatisowner,ifthereisanowner,setsnMAbort_false.Nexttherearew(zeroormore)waitcycles,withDRAGONPROJECTFORINTERNALXEROXUSEONLYxgy gg!x%gg'_y(Fgg),x*gyg+f tgEx_'WW b"$),0]2 59;=]!"F'+/3;#=[ #%+p. 6h9.RU;tj #&)M.147:l>SOqwC$zzL xId%a)+. 58:o=?G B !7#v'-k047:} FX&#C%(+G1048l; Dov "( )E-02l49D?C  !x$&Q).168};1=+@oAb?l%!> $a),.%1 3;59;s?=@J ').`0357 ?r; _ #$&(+{6 x4'h !&(,x.a/5:=2=xv"'|).365708/16%x! "%(R. 5T8:R=-kp_!a$'+.K3 ;h>+)g.$ *.0(26]9-@p'  u%+u-2b5p: ;&r{R $j%+a-02x47<;>@e$qq   '.`25h6 >"A?M NG! (C).916A9&=q 8  a$(,/t168;+?hE!{ x "]$,@0168:b>@" !')z/ 6lA# &(d,-2O68[:?}~%@ ,47> %i"%_*-5}:M= v2!#:$m)+-0y4N7&8=*> >( ?$-'+-G.2'37:?y /%'.*0y47 BTVm$jDRAGONMBUSSPECIFICATIONS11theslavesettingMCmd_NoOp.Cycles5+wthrough8+waredatatransfercyclesinwhichtheslavesetsMCmdAB_DataTransport;MDataAB_data;MParity_parity.DuringtheBofcycle6+wthemastermaydropMRq,andifitdoes,thearbiterdropsMGntduringtheAof8+w.NotethattheminimumnumberofcyclesforReadQuadis6,assumingzeromemorywait.4.3WriteQuadFigure4showsthetimingforWriteQuad.Cycles0through2aredevotedtoarbitrationasusual.DuringtheAofcycle3themastersetsMCmdAB_WriteQuad;MDataAB_WQAddress;nMShared_true.Nexttherearew(zeroormore)waitcycleswherethemasterassertsMDataABandMParityandthememoryassertsMCmdAB.Cycle4+wisadatatransportcycle,withthememoryassertingMCmdABandthemasterassertingMDataAB.Duringcycle4,nMSharedissettofalseifthereisamatch,regardlessofthevaluecurrentlyassertedforMCmdAB.Cycles5+w,6+wand7+wareagaindatatransportcycleswiththememoryassertingMCmdandthemastersupplyingthedata.DuringtheBofcycle5+wthemastermaydropMRq,andifitdoes,thearbiterdropsMGntduringtheAof7+w.NotethattheminumumnumberofcyclesforWriteQuadis5.4.4WriteSingleFigure5showsthetimingforWriteSingle.Cycles0through2aredevotedtoarbitration.DuringtheBofcycle2themastermaysetMRq_false,andifitdoes,thearbiterdropsMGntduringtheAofcycle4.Cycle3isthefirsttransactioncycle.DuringphaseAthemastersetsMCmdAB_WriteSingle;MDataAB_WSAddress;andnMShared_true.DuringtheAofcycle4themastersetsMCmdAB_DataTransport;MDataAB_WSData;MParity_parity.AlsoatthistimeifthereisamatchoneormoreslavessetnMShared_false.4.5IOReadFigure6showsthetimingforIORead.Arbitrationtakesplaceduringcycles0through2.DuringtheAofcycle3themastersetsMCmdAB_IORead;MDataAB_IOAddress.ThenfollowwcyclesduringwhichtheslaveusesthebusforcommandsotherthanIODone(thesecyclesmaybeidle).Asusual,wiszeroormore.DuringtheAofcycle4+wtheslavesetsMCmdAB_IODone;andMDataAB_IOData.Cycles5+wthrough7+wmaybeidlecycles,withthemastersettingMCmdAB_NoOp.DuringtheBofcycle5+wthemastermaysetMRq_falseandifitdoes,thearbitersetsMGnt_falseduringtheAof7+w.4.6IOWriteFigure7showsthetimingforIOWrite.LikeIORead,IOWritealsoisflowcontrolledanditstimingissimilar.Cycles0through2areforarbitrationasusual.DRAGONPROJECTFORINTERNALXEROXUSEONLYxgy gg!x%gg'_y(Fgg),x*gyg+f tgEx_//#'+S0y36;9.>']Y7&5 08;[v8!%P',1/>269d:<-?Z9S)b"2#%xW;*! &m(F,^.57O8?VOTo{QxOy^v"E$ ,1 2L78;-@oM UKVe!7#(1*2 :sI #"&5),-1+27:>H0 ^#(J*->26>HF`m!$&,Y18;V=DA!$&E-.0257H:>P8"&+)-/0;H!&-'+.5C6{6 x4/Pa""$c ,1/2h78;4@o2 t5 $%='+.159=;=F>0A"2$&'+J.eWi #}',,/1T37:], > &)K149H;=>+a " ,4:@)o7*"#%)'+-t046>{$xx!EP"$B*Q 1v48<@ VP "F$),}4:s3 x$#r'+.1b4E69;9t"%'+-1~24R7I9=UTD[!$,[2J5<=F%"$'+/ 1s5:]$J!%Q',!/%1C59&;=?>AS %6')"*{x }:N"%3+/*4:=r?  dP%)w*/13l5 y /%'.*0y47ATVm$ DRAGONMBUSSPECIFICATIONS12DuringtheAofcycle3themastersetsMCmdAB_IOWrite;MDataAB_IOAddress.DuringtheAofcycle4themastersetsMDataAB_IOData.DuringthisphasetheslavesetsMCmdAB_IODoneortoNoOp.IfitsetsIODonethetransactionisover.IfIODoneisnotassertedduringcycle4thenthefollowingwcyclesareusedbytheslaveforcommandsotherthanIODone.DuringtheAofcycle5+wtheslavesetsMCmdAB_IODone.Cycles6+wthrough8+wmaybeidle,withthemastersettingMCmdAB_NoOp.DuringtheBof6+wthemastersetsMRq_false,andifitdoesthearbitersetsMGnt_falseduringtheAof8+w.AppendixA.IOAddressSpaceDefinitionTheIOaddressspaceiscarvedupintodisjoint,contiguouspieceswithatmostonedevicerespondingtoeachpiece.Currently,theonlypieceassignedbelongstotheMapprocessor.AddressrangeDevice0_2||vp||+1-1Mapprocessor(||vp||isthenumberofbitsneededtorepresentavirtualpage)DRAGONPROJECTFORINTERNALXEROXUSEONLYxgy gg!x%gg'_y(Fgg),x*gyg+f tgEx_/D  ""$)j,H4E:s] !\$&(-/7k=U[ D&+-t/:467:D?Z9 JW4!&e)+).]068{<>VpH G#'?-25 68<?T`]#K'+_04R7i9m<?Rq%(*,./36:=kQj! h!$z),1]35I7zJ`J!% xFxw( $')/ 6:=->EV !&C ,/;2V5;d@oCA {A$A$(x>|>x>.y?}k??yt??x>>(+1p2>>3x4C>>45U68=?|<;6(./4;y /%'.*0y47DTVm$DRAGONMBUSSPECIFICATIONS13BusCouplerROMBootOthersInterfaceEthernetDiskInterfaceI/OprocessorVME BusCacheMap Processorwith Map CacheModuleMemoryDragon ModuleDragon ModuleIFUEUFlt. Mult.Flt. AddInstr.CacheDataCacheDragon ProcessorDragon ModuleMemoryModuleMemoryModuleControllerDisplayM BusFigure 1. A Dragon ClusterDRAGONPROJECTFORINTERNALXEROXUSEONLYxgy gg!x%gg'_y(Fgg),x*gyg+f tgE~#`$#[$r#[ $#[$r\^f\\Iks#Ye$#U$r#U$r#T $VW#R$#Nl$r#Nl$r#NI $\P Q SI[P $?P$r[P$r[T$[W, $?WP$r[WP$r[[$ Y XI[] $?]$r[]$r[bI$ ` ^[Je?`r$?Yer$?Rr$]r$W,r$Pr$'xbI$'xY$0\Y$'xYe $)]#]r$'xT V$'xI$ 4I$ 'xI y$)O )NI B$W, $B$I$ VMAI$ VB$I @$EyOeEyQ;yP$4Oe$;y kV# ? !z$? $r?!V$?!V$?j$r?G!z$# ?5$9#N$(xN$(8$83$83$>$#;d;d$0H$ $#25$/O$/O$/+$x) ,$&k$&k$&G$$$$$c$x xC,$ ]$x+$%?>$%?83$+83$%?8$&;&:H%?3$%?-$+-$%?,$&0&/+)9$A?$.[E ?G!V$?!z$2$.2j$r2 $r+;dy$/@0k$ +0Hy$/@5 9$2$2 $0\] $;y<$Ey=Ey;dB$5 @$MA5$ VB$5$ VB$C, $;y($Ey)Ey'dB$! @$MA!$ VB$!$ VB$/+ $D D=$ ?c$?1$ VOz1$ V?$;yr$$#*y /%'.*0y47]TVm$CDRAGONMBUSSPECIFICATIONS14Figure 2. Timing for Bus Arbitrationconditionally retain bus => master: MNewRq _ TRUE; <>arbiter: MGnt _ TRUE;arbiter: latch request;requestor: Mrq _ TRUE;5+w4+w3+w2+w(w>=0)w cycles1ABABABABABAB0PhaseCycleBA<><><>DRAGONPROJECTFORINTERNALXEROXUSEONLYxgy gg!x%gg'_y(Fgg),x*gyg+f tgE~"x$$?lWAJL-$&?-$&~ [3 [7 [; [@e C E~ [IH4+1 1d:$86d 5:$=: :H:$A?H >:$EC C,:$JeH, G:$ L:$ [M[Q S>;$ P>;$ ?QLN=38"4Oy /%'.*0y47TVm$DRAGONMBUSSPECIFICATIONS15Figure 3. Timing for ReadQuadslave: {MCmdAB _ DataTransport; MDataAB _ RQData3; MParity _ parity} arbiter: MGnt _ FALSE;slave: {MCmdAB _ DataTransport; MDataAB _ RQData2; MParity _ parity}slave: {MCmdAB _ DataTransport; MDataAB _ RQData1; MParity _ parity}slave: {MCmdAB _ DataTransport; MDataAB _ RQData0; MParity _ parity}slave: MCmdAB _ NoOp;slave: {MCmdAB _ NoOp; match => nMShared _ FALSE; owner => nMAbort _ FALSE}master: {MCmdAB _ ReadQuad; MDataAB _ RQAddress; nMShared _ TRUE; nMAbort _ TRUE}8+w7+w6+w432w cycles(w>=0)BABABAarbiter: MGnt _ TRUE;requestor: Mrq _ TRUE;5+w1ABABABABABAB0PhaseCycleBAmaster: MRq _ FALSE;DRAGONPROJECTFORINTERNALXEROXUSEONLYxgy gg!x%gg'_y(Fgg),x*gyg+f tgE~!\&_+kD/D4D9=3KAQ~ "% "*+ ". "; "@e "D 8 7 ,?W$~-/ (?W$)+G $?W$$&FL!$2!$2~ "3 "IH4+1 1d?W$86d 5?W$=: :H?W$A?H >?W$EC C,?W$JeH, G?W$ L?W$ "M"Q[SB$[PB$ QLN-y /%'.*0y47TVm$7DRAGONMBUSSPECIFICATIONS16Figure 4. Timing for WriteQuadmaster: MDataAB _ WQData0; memory: MCmdAB _ DataTransport; slave: match => nMShared _ FALSE;master: MRq _ FALSE;master: MDataAB _ WQData1; memory: MCmdAB _ DataTransport;master: MDataAB _ WQData2; memory: MCmdAB _ DataTransport;master: MDataAB _ WQData0; memory: MCmdAB _ NoOp;master: {MCmdAB _ WriteQuad; MDataAb _ WQAddress; nMShared _ TRUE}4+ww cycles(w>=0)ABCyclePhase0BABABABABABA15+wrequestor: Mrq _ TRUE;arbiter: MGnt _ TRUE;ABAB236+w7+wmaster: MDataAB _ WQData3; memory: MCmdAB _ DataTransport; arbiter MGnt _ FALSE;DRAGONPROJECTFORINTERNALXEROXUSEONLYxgy gg!x%gg'_y(Fgg),x*gyg+f tgE~!\x8bx2x4O=x/=x=z4xAB~7=3;~NLQ"PD$"SD$ QM wLA$ wGA$H,Je wC,A$CE w>A$?HA w:HA$:= w5A$6d8 w1dA$14+IH3 &k$-[&k$-xLxF~+G) w(A$/- w,A$D@e.*+x+kVy /%'.*0y47~TVm$#DRAGONMBUSSPECIFICATIONS17ABCyclePhase0BABABABA1requestor: Mrq _ TRUE;arbiter: MGnt _ TRUE;23Figure 5. Timing for WriteSingle4master: MRq _ FALSE;master: {MCmdAB _ WriteSingle; MDataAB _ WSAddress; nMShared _ TRUE}master: {MCmdAB _ DataTransport; MDataAB _ WSData; MParity _ parity} slave: match => nMShared _ FALSE;DRAGONPROJECTFORINTERNALXEROXUSEONLYxgy gg!x%gg'_y(Fgg),x*gyg+f tgE~NLQ"PG$"SG$ QM wLC$ wGC$H,Je wC,C$CE w>C$?HA w:HC$:=IH 83$[83$xLxF~D@e$<xD%xADx=ziy /%'.*0y47dTVm$DRAGONMBUSSPECIFICATIONS187+w6+w32BABAarbiter: MGnt _ TRUE;requestor: Mrq _ TRUE;5+w1ABABABABABAB0PhaseCycleBA(w>=0)w cycles4+wmaster: MRq _ FALSE;master: {MCmdAB _ IORead; MDataAB _ IOAddress}slave: {MCmdAB _ anything but IODone; M bus lines other than MCmdAB _ anything}master: MCmdAB _ NoOp;master: MCmdAB _ NoOp; arbiter MGnt _ FALSE;master: MCmdAB _ NoOp;slave: {MCmdAB _ IODone; MDataAB _ IOData}Figure 6. Timing for IOReadDRAGONPROJECTFORINTERNALXEROXUSEONLYxgy gg!x%gg'_y(Fgg),x*gyg+f tgE~*+.@eD w,A$-/ w(A$)+GxFxL[&k$- &k$-~3IH4+1 w1dA$86d w5A$=: w:HA$A?H w>A$EC wC,A$JeH, wGA$ wLA$M Q"SD$"PD$QLN;=3~7x2xA.x=Ox0$x+k/x4Ox9*~!\y /%'.*0y47TVm$"DRAGONMBUSSPECIFICATIONS197+w6+w32BABAarbiter: MGnt _ TRUE;requestor: Mrq _ TRUE;5+w1ABABABABABAB0PhaseCycleBAmaster: MCmdAB _ NoOp;Figure 7. Timing for IOWritemaster: MCmdAB _ NoOp; arbiter MGnt _ FALSE;AB8+ww cycles(w>=0)4master: {MCmdAB _ IOWrite; MDataAB _ IOAddress}slave: {MCmdAB _ anything but IODone; M bus lines other than MCmdAB _ anything}master: MDataAB _ IOData; slave: MCmdAB _ NoOp or IODone;master: MRq _ FALSE;slave: {MCmdAB _ IODone; MDataAB _ undefined}master: MCmdAB _ NoOp;DRAGONPROJECTFORINTERNALXEROXUSEONLYxgy gg!x%gg'_y(Fgg),x*gyg+f tgE~*+.@eD w,A$-/ w(A$)+GxFxL[!$2 !$2~3IH4+1 w1dA$86d w5A$=: w:HA$A?H w>A$EC wC,A$JeH, wGA$ wLA$M Q"SD$"PD$QLNx0$~!\x&/~&$ w$A$%87~;xA/x8Ox=z<x-x4O-x+ky /%'.*0y47TVm$7 TIMESROMAN TIMESROMAN  TIMESROMAN MATH TIMESROMAN TIMESROMANY TIMESROMAN TIMESROMANLOGO HELVETICAMATH HELVETICA HELVETICA HELVETICA HELVETICA TIMESROMAND & *" `+2: YE O X{\ `Bbnehjmpj/tr? []<>mbusspecs.tioga$Monday, January 21, 1985 3:34 pm PST