circuit[Lambda _ 1, Temp _ 100] = { Vdd: node; ! ThymeBasics ! CMOS2.0u100C powerSupply: voltage[Vdd, Gnd] = 5.0; ?: Stray[Gnd| anD_46, pnD_8, aM_41, pM_28, aM2_438, pM2_158]; q: node; ?: Stray[q| anD_43, pnD_30, aP_107, pP_92, aM_98, pM_64, apD_19, ppD_15]; nq: node; ?: Stray[nq| anD_43, pnD_30, aP_105, pP_88, aM_72, pM_44, apD_22, ppD_17]; n: node; bit: node; ?: Stray[bit| anD_19, pnD_15, aM_178, pM_124]; access0: node; ?: Stray[access0| aP_82, pP_74, aM_90, pM_56, aM2_300, pM2_156]; ?: Stray[Vdd| aM_90, pM_56, anD_84, pnD_50, apD_225, ppD_138, aM2_450, pM2_146]; nbit: node; ?: Stray[nbit| aM_178, pM_124, anD_19, pnD_15]; Q1: ETran[q,nq,Gnd| W_7]; Q2: ETran[nq,q,Gnd| W_7]; Q3: CTran[nq,Vdd,q| W_3, L_5]; Q4: ETran[access0,bit,q| W_3]; Q5: CTran[q,nq,Vdd| W_3, L_5]; Q6: ETran[access0,nbit,nq| W_3]; ?: voltage[bit, Gnd] = 0.0V; ?: voltage[nbit, Gnd] = 3.0V; ?: RectWave[access0 | period _ 100ns, width _ 50ns, tRise _ 10ns, tFall _ 10ns, tDelay _ 20ns]; }; ic[nq _ 0V]; PLOT["CMOS SRamWriteTest (2 microns, 100 C) ic[nq _ 0] bit=0.0V nbit=3.0V", :1ns, -1, 6, powerSupply^: -1mA, access0, bit, nbit, q, nq]; RUN[tMax _ 50ns]; Œ[]<>SRamTestCell.thy, Written by Spinifex, February 26, 1985 9:39:42 pm PST Last Edited by: Sindhu, February 26, 1985 11:02:17 pm PST ΚΌ– "Cedar" style˜J™KJ™9unitšœ#˜#Kšœ ˜ Kšœ ˜ KšœΟsœ˜Kšœ%˜%K˜Icode˜=L˜RL˜TL˜L˜9L˜OL˜PL˜;L˜L˜L˜L˜L˜L˜ L˜L˜L˜_L˜L˜L˜L˜ LšΟkœœ~˜ˆJšžœ˜——…—tΌ