circuit[Lambda _ 1, Temp _ 100] = { Vdd: node; ! ThymeBasics ! CMOS2.0u100C powerSupply: voltage[Vdd, Gnd] = 5.0; andout: node; ?: Stray[andout| anD_20, pnD_14, apD_20, ppD_14, aM_66, pM_48, aP_70, pP_70]; nD: node; ?: Stray[nD| anD_20, pnD_14, apD_20, ppD_14, aM_70, pM_50, aP_224, pP_188]; n1: node; n2: node; ?: Stray[n2| anD_12, pnD_6]; n3: node; ?: Stray[n3| anD_20, pnD_14, apD_41, ppD_30, aM_154, pM_104, aP_96, pP_92]; n4: node; ?: Stray[n4| anD_16, pnD_8]; clock: node; ?: Stray[clock| aP_186, pP_190]; ?: Stray[Vdd| apD_139, ppD_102, anD_64, pnD_64, aM_464, pM_298]; n5: node; ?: Stray[n5| anD_20, pnD_14, aP_162, pP_160, aM_76, pM_54, apD_19, ppD_15]; ?: Stray[Gnd| anD_147, pnD_103, aP_68, pP_36, aM_536, pM_356]; match: node; ?: Stray[match| anD_19, pnD_15, aM_50, pM_36, aP_416, pP_416]; D: node; ?: Stray[D| anD_48, pnD_32, aP_228, pP_220, aM_192, pM_136, apD_39, ppD_29]; Q1: ETran[D,nD,Gnd]; Q2: ETran[andout,D,Gnd| W_8]; Q3: CTran[n3,Vdd,andout]; Q4: ETran[nD,D,n2]; Q5: ETran[n3,andout,Gnd]; Q6: CTran[match,Vdd,n3]; Q7: ETran[clock,n3,n4]; Q8: ETran[n5,n5,Gnd]; Q9: CTran[Gnd,Vdd,n5| W_3, L_8]; Q10: CTran[nD,Vdd,D| W_3, L_8]; Q11: ETran[n5,n2,Gnd]; Q12: CTran[D,Vdd,nD]; Q13: ETran[match,Gnd,n4]; Q14: CTran[clock,Vdd,n3]; Q15: CTran[clock,Vdd,D]; Q16: ETran[nD,match,Gnd| W_3]; ?: capacitor[match, Gnd] = .5pF; ?: RectWave[clock | period _ 100ns, width _ 50ns, tRise _ 10ns, tFall _ 10ns, tDelay _ 5ns]; }; ic[match _ 5V]; PLOT["CMOS TestKillEntry .5 pf match 3/2 pd (2 microns, 100 C)", :1ns, -1, 6, clock, match, D, nD, andout]; RUN[tMax _ 50ns]; []<>TestKillEntry.thy, Written by Spinifex, March 6, 1985 3:49:30 pm PST Last Edited by: Sindhu, March 6, 1985 4:03:53 pm PST -- ALIAS[ n1, n1] --  "Cedar" styleJHJ4unit##K K KsK%b&Icode[LULL L&LUL&L-L@LUL>LKLULLLLLLLLL LLLLLLLLL L\LLLJJkakJLL*