circuit[Lambda _ 1, Temp _ 100] = { Vdd: node; ! ThymeBasics ! CMOS2.0u100C powerSupply: voltage[Vdd, Gnd] = 5.0; n1: node; ?: Stray[n1| anD_36, pnD_18, aM_180, pM_98]; ?: Stray[Gnd| anD_73, pnD_42, aM_235, pM_104]; n2: node; ?: Stray[n2| aM2_100, pM2_58]; n3: node; ?: Stray[n3| aM2_100, pM2_58]; n4: node; ?: Stray[n4| aP_64, pP_68, anD_60, pnD_44]; D: node; ?: Stray[D| anD_60, pnD_46, aP_92, pP_96]; $D/nM$: node; ?: Stray[$D/nM$| aM_192, pM_104, anD_40, pnD_28]; n5: node; ?: Stray[n5| aP_42, pP_46, anD_34, pnD_34]; $nD/M$: node; ?: Stray[$nD/M$| anD_62, pnD_46, aM_188, pM_102]; mAccess: node; ?: Stray[mAccess| aP_50, pP_54]; match: node; ?: Stray[match| anD_54, pnD_46, aP_134, pP_138]; n6: node; ?: Stray[n6| aM2_88, pM2_52]; bit: node; ?: Stray[bit| anD_20, pnD_14, aM_180, pM_98]; nbit: node; ?: Stray[nbit| anD_20, pnD_14, aM_180, pM_98]; $Q-12$: node; ?: Stray[$Q-12$| anD_54, pnD_41, aP_34, pP_38]; nQ: node; ?: Stray[nQ| aP_34, pP_38, anD_55, pnD_43]; Q1: ETran[n4,Gnd,D| W_8]; Q2: ETran[mAccess,$nD/M$,n4]; Q3: ETran[mAccess,$D/nM$,D]; Q4: ETran[n5,match,Gnd| W_6]; Q5: ETran[D,n4,Gnd| W_8]; Q6: ETran[D,$D/nM$,n5]; Q7: ETran[n4,$nD/M$,n5]; Q8: ETran[match,bit,$Q-12$]; Q9: ETran[match,nbit,nQ]; Q10: ETran[nQ,n1,$Q-12$| W_7]; Q11: ETran[$Q-12$,nQ,n1| W_7]; ?: capacitor[match, Gnd] = 0.9pF; ?: capacitor[bit, Gnd] = 1.0pF; ?: capacitor[nbit, Gnd] = 1.0pF; ?: RectWave[$D/nM$ | period _ 100ns, width _ 50ns, tRise _ 10ns, tFall _ 10ns, tDelay _ 0ns]; }; ic[D _ 5V, match _ 5V, Q _ 5V, bit _ 5V, nbit _ 5V]; PLOT["CMOS src (2 microns, 100 C)", :1ns, -1, 6, powerSupply^: -1mA, match, $D/nM$, bit, nbit]; RUN[tMax _ 50ns]; ž[]<>TestDCamDRamCell.thy, Written by Spinifex, March 1, 1985 10:02:14 pm PST Last Edited by: Sindhu, March 1, 1985 10:19:20 pm PST -- ALIAS[ n1, n1] -- Κε– "Cedar" style˜J™LJ™5unitšœ#˜#Kšœ ˜ Kšœ ˜ KšœΟsœ˜Kšœ%˜%Icode™L˜6L˜.L˜(L˜(L˜5L˜3L˜?L˜5L˜?L˜/L˜=L˜'L˜8L˜:L˜=L˜5L˜L˜L˜L˜L˜L˜L˜L˜L˜L˜L˜L˜!L˜L˜ L˜]L˜L˜L˜4JšΟkœœU˜_Jšžœ˜L˜——…—jν