?: Stray[Vdd| apD�, ppD�, anD�, pnD�, aM�, pM�];

-- ALIAS[ n1, n1] --

n1: node;

?: Stray[Gnd| aM�, pM�, anD�, pnD�];

out: node; ?: Stray[out| anD�, pnD�, aM�, pM�, apD�, ppD�];

slowout: node; ?: Stray[slowout| anD�, pnD�, aM�, pM�, apD�, ppD�];

in: node; ?: Stray[in| aP�, pP�];

n2: node;

slowmatch: node; ?: Stray[slowmatch| anD�, pnD�, aM�, pM�, aP�, pP�];

match: node; ?: Stray[match| aP�, pP�, anD�, pnD�, aM�, pM�];

Q1: ETran[match,out,Gnd];

Q2: CTran[match,Vdd,out];

Q3: CTran[slowmatch,Vdd,slowout];

Q4: ETran[slowmatch,slowout,Gnd];

Q5: ETran[in,match,Gnd| W𡤆];

Q6: ETran[in,Gnd,slowmatch| L𡤄];

?: capacitor[match, Gnd] = 1.0pF;

?: capacitor[slowmatch, Gnd] = 1.0pF;

?: RectWave[in | period ← 100ns, width ← 50ns, tRise ← 10ns, tFall ← 10ns, tDelay ← 0ns];

};

ic[match ← 5V, slowmatch ← 5V];

PLOT["CMOS TestDCacheArray (2 microns, 100 C)", :1ns, -1, 6, powerSupply^: -1mA, in, match, slowmatch, out, slowout];

RUN[tMax ← 50ns];