[]<>SRamTestCell.thy, Written by Spinifex, February 26, 1985 9:39:42 pm PST
Last Edited by: Sindhu, February 26, 1985 11:02:17 pm PST
circuit[Lambda ← 1, Temp ← 100] = {
Vdd: node;
! ThymeBasics
! CMOS2.0u100C
powerSupply: voltage[Vdd, Gnd] = 5.0;
?: Stray[Gnd| anD�, pnD𡤈, aM�, pM�, aM2�, pM2�];
q: node; ?: Stray[q| anD�, pnD�, aP�, pP�, aM�, pM�, apD�, ppD�];
nq: node; ?: Stray[nq| anD�, pnD�, aP�, pP�, aM�, pM�, apD�, ppD�];
n: node;
bit: node; ?: Stray[bit| anD�, pnD�, aM�, pM�];
access0: node; ?: Stray[access0| aP�, pP�, aM�, pM�, aM2�, pM2�];
?: Stray[Vdd| aM�, pM�, anD�, pnD�, apD�, ppD�, aM2�, pM2�];
nbit: node; ?: Stray[nbit| aM�, pM�, anD�, pnD�];
Q1: ETran[q,nq,Gnd| W𡤇];
Q2: ETran[nq,q,Gnd| W𡤇];
Q3: CTran[nq,Vdd,q| W𡤃, L𡤅];
Q4: ETran[access0,bit,q| W𡤃];
Q5: CTran[q,nq,Vdd| W𡤃, L𡤅];
Q6: ETran[access0,nbit,nq| W𡤃];
?: voltage[bit, Gnd] = 0.0V;
?: voltage[nbit, Gnd] = 3.0V;
?: RectWave[access0 | period ← 100ns, width ← 50ns, tRise ← 10ns, tFall ← 10ns, tDelay ← 20ns];
};
ic[nq ← 0V];
PLOT["CMOS SRamWriteTest (2 microns, 100 C) ic[nq ← 0] bit=0.0V nbit=3.0V", :1ns, -1, 6, powerSupply^: -1mA, access0, bit, nbit, q, nq];
RUN[tMax ← 50ns];