Vdd: node;

! ThymeBasics

! CMOS2.0u25C

powerSupply: voltage[Vdd, Gnd] = 5.0;

?: Stray[Vdd| anD←N*16, pnD←N*16, aM←N*234, pM←N*156, apD←N*284, ppD←N*88, aM2←N*2136, pM2←N*550];

Vpbias: node; ?: Stray[Vpbias| aM←N*163, pM←N*114, aP←N*42, pP←N*42];

-- ALIAS[ n1, n1] --

n1: node;

linesel: node; ?: Stray[linesel| anD←N*32, pnD←N*16, apD←N*80, ppD←N*32, aM←N*172, pM←N*116, aM2←N*37, pM2←N*26];

?: Stray[Gnd| aM←N*1212, pM←N*246, anD←N*624, pnD←N*178, apD←N*16, ppD←N*16, aM2←N*2136, pM2←N*550];

nphA: node; ?: Stray[nphA| aP←N*42, pP←N*42, aM←N*163, pM←N*114];

nlinesel: node; ?: Stray[nlinesel| aM2←N*25, pM2←N*20, aP←N*380, pP←N*274, apD←N*107, ppD←N*26, aM←N*98, pM←N*72, anD←N*130, pnD←N*36];

n2: node; ?: Stray[n2| anD←N*190, pnD←N*38];

n3: node; ?: Stray[n3| anD←N*180, pnD←N*36];

n4: node; ?: Stray[n4| anD←N*190, pnD←N*38];

n5: node; ?: Stray[n5| aM2←N*752, pM2←N*384];

n6: node; ?: Stray[n6| anD←N*190, pnD←N*38];

n7: node; ?: Stray[n7| anD←N*190, pnD←N*38];

n8: node; ?: Stray[n8| anD←N*190, pnD←N*38];

-- ALIAS[ input, input, $adrs-1$] --

input: node; ?: Stray[input| aM←N*1679, pM←N*1120, aP←N*336, pP←N*336];

n9: node; ?: Stray[n9| anD←N*190, pnD←N*38];

-- ALIAS[ phB, $adrs-2$] --

phB: node; ?: Stray[phB| aM←N*166, pM←N*116, aP←N*42, pP←N*42];

n10: node; ?: Stray[n10| anD←N*190, pnD←N*38];

Q1: CTran[nlinesel,linesel,Vdd| W←N*16];

Q2: CTran[nlinesel,Vdd,linesel| W←N*16];

Q3: ETran[nlinesel,linesel,Gnd| W←N*6];

Q4: ETran[nlinesel,Gnd,linesel| W←N*6];

Q5: CTran[Vpbias,nlinesel,Vdd| W←N*10];

Q6: CTran[nphA,Vdd,nlinesel| W←N*10];

Q7: ETran[input,n2,n8| W←N*10];

Q8: ETran[input,n3,n4| W←N*10];

Q9: ETran[input,n4,n7| W←N*10];

Q10: ETran[input,n6,nlinesel| W←N*10];

Q11: ETran[input,n7,n6| W←N*10];

Q12: ETran[input,n8,n10| W←N*10];

Q13: ETran[input,n9,n2| W←N*10];

Q14: ETran[phB,Gnd,n9| W←N*10];

Q15: ETran[input,n10,n3| W←N*10];

?: RectWave[phB | period ← 100ns, width ← 30ns, tRise ← 10ns, tFall ← 10ns, tDelay ← 30ns];

?: RectWave[nphA | OnLevel ← 0V, OffLevel ← 5V, period ← 100ns, width ← 30ns, tRise ← 10ns, tFall ← 10ns, tDelay ← 0ns];

?: voltage[Vpbias, Gnd] =5;

?: voltage[input, Gnd] =5;

?: capacitor[linesel, Gnd] = 1.6pF;

};

PLOT["CMOS AdrsDecoder 10/2 transistors", :1ns, -1, 6, phB, nphA, nlinesel, linesel];

RUN[tMax ← 60ns];