[Indigo]<Dragon>June87>June87Test.mesa!3

June87Test.mesa

Barth, August 12, 1986 11:17:18 am PDT

DIRECTORY Core, CoreClasses, CoreCreate, Ports, Rosemary, RosemaryUser;

June87Test: CEDAR PROGRAM

IMPORTS CoreClasses, CoreCreate, Ports, Rosemary, RosemaryUser =

BEGIN

Vcc: NAT;

Gnd: NAT;

BootButton: NAT;

PowerNormal: NAT;

TimeBase: NAT;

LED1: NAT;

LED2: NAT;

LED3: NAT;

Init: PROC [ct: Core.CellType] = {

Vcc ← Ports.PortIndex[ct.public, "Vdd"];

Gnd ← Ports.PortIndex[ct.public, "Gnd"];

BootButton ← Ports.PortIndex[ct.public, "BootButton"];

PowerNormal ← Ports.PortIndex[ct.public, "PowerNormal"];

TimeBase ← Ports.PortIndex[ct.public, "TimeBase"];

LED1 ← Ports.PortIndex[ct.public, "LED1"];

LED2 ← Ports.PortIndex[ct.public, "LED2"];

LED3 ← Ports.PortIndex[ct.public, "LED3"];

[] ← Rosemary.SetFixedWire[ct.public[Vcc], H];

[] ← Rosemary.SetFixedWire[ct.public[Gnd], L];

[] ← Ports.InitTesterDrive[wire: ct.public[BootButton], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[PowerNormal], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[TimeBase], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[LED1], initDrive: none];

[] ← Ports.InitTesterDrive[wire: ct.public[LED2], initDrive: none];

[] ← Ports.InitTesterDrive[wire: ct.public[LED3], initDrive: none];

[] ← RosemaryUser.TestProcedureViewer[name: "June87 Tester", cellType: ct, testButtons: LIST["BasicTest"], displayWires: RosemaryUser.DisplayCellTypePortLeafWires[ct]];

};

BasicTest: RosemaryUser.TestProc = {

Cycles: PROC [count: NAT] = {

FOR cycle: NAT IN [0..count) DO

p[TimeBase].b ← TRUE;

Eval[];

p[TimeBase].b ← FALSE;

Eval[];

ENDLOOP;

};

p[BootButton].b ← TRUE;

p[PowerNormal].b ← TRUE;

Cycles[10];

p[BootButton].b ← FALSE;

Cycles[100];

};

BusBuffer

BusBufferName: Core.ROPE = Rosemary.Register[roseClassName: "BusBuffer", init: BusBufferInit, evalSimple: BusBufferSimple];

BusBufferVdd: NAT = 0;

BusBufferPadVdd: NAT = 1;

BusBufferGnd: NAT = 2;

BusBufferPadGnd: NAT = 3;

BusBufferClock: NAT = 4;

BusBuffernClock: NAT = 5;

BusBufferData: NAT = 6;

BusBufferDataIn: NAT = 7;

BusBufferDataOut: NAT = 8;

BusBufferBus1: NAT = 9;

BusBufferBus2: NAT = 10;

BusBufferBus3: NAT = 11;

BusBufferIn1: NAT = 12;

BusBufferIn2: NAT = 13;

BusBufferIn3: NAT = 14;

BusBufferOut1: NAT = 15;

BusBufferOut2: NAT = 16;

BusBufferOut3: NAT = 17;

BusBufferState: TYPE = REF BusBufferStateRec;

BusBufferStateRec: TYPE = RECORD [

lastClock: Ports.Level,

dataOutLatch: ARRAY [0..32) OF Ports.Level,

dataInLatch: ARRAY [0..32) OF Ports.Level,

latchOut: ARRAY [0..3) OF Ports.Level,

latchIn: ARRAY [0..3) OF Ports.Level];

BusBuffer: PUBLIC PROC RETURNS [ct: Core.CellType] = {

p: Core.Wire ← CoreCreate.WireList[LIST["Vdd", "PadVdd", "Gnd", "PadGnd", "Clock", "nClock", CoreCreate.Seq["Data", 32], CoreCreate.Seq["DataIn", 32], CoreCreate.Seq["DataOut", 32], "Bus1", "Bus2", "Bus3", "In1", "In2", "In3", "Out1", "Out2", "Out3"]];

ct ← CoreClasses.CreateUnspecified[name: BusBufferName, public: p];

[] ← Ports.InitPort[wire: p[BusBufferClock], levelType: l];

[] ← Ports.InitPort[wire: p[BusBuffernClock], levelType: l];

FOR i: NAT IN [0..32) DO

[] ← Ports.InitPort[wire: p[BusBufferData][i], levelType: l];

[] ← Ports.InitPort[wire: p[BusBufferDataIn][i], levelType: l];

[] ← Ports.InitPort[wire: p[BusBufferDataOut][i], levelType: l];

ENDLOOP;

FOR i: NAT IN [0..3) DO

[] ← Ports.InitPort[wire: p[BusBufferBus1+i], levelType: l];

[] ← Ports.InitPort[wire: p[BusBufferIn1+i], levelType: l];

[] ← Ports.InitPort[wire: p[BusBufferOut1+i], levelType: l];

ENDLOOP;

};

BusBufferInit: Rosemary.InitProc = {

stateAny ← NEW[BusBufferStateRec];

};

BusBufferSimple: Rosemary.EvalProc = {

state: BusBufferState ← NARROW[stateAny];

IF p[BusBufferClock].l=H AND state.lastClock=L THEN {

FOR i: NAT IN [0..32) DO

state.dataOutLatch[i] ← p[BusBufferData][i].l;

state.dataInLatch[i] ← p[BusBufferDataIn][i].l;

ENDLOOP;

FOR i: NAT IN [0..3) DO

state.latchOut[i] ← p[BusBufferBus1+i].l;

state.latchIn[i] ← p[BusBufferIn1+i].l;

ENDLOOP;

};

state.lastClock ← p[BusBufferClock].l;

FOR i: NAT IN [0..32) DO

p[BusBufferData][i].l ← L;

p[BusBufferData][i].d ← IF state.dataInLatch[i]#H THEN drive ELSE none;

p[BusBufferDataOut][i].l ← L;

p[BusBufferDataOut][i].d ← IF state.dataOutLatch[i]#H THEN drive ELSE none;

ENDLOOP;

FOR i: NAT IN [0..3) DO

p[BusBufferBus1+i].l ← L;

p[BusBufferBus1+i].d ← IF state.latchIn[i]#H THEN drive ELSE none;

p[BusBufferOut1+i].l ← L;

p[BusBufferOut1+i].d ← IF state.latchOut[i]#H THEN drive ELSE none;

ENDLOOP;

};

BusInterface

BusInterfaceName: Core.ROPE = Rosemary.Register[roseClassName: "BusInterface", init: BusInterfaceInit, evalSimple: BusInterfaceSimple];

BusInterfaceVdd: NAT = 0;

BusInterfacePadVdd: NAT = 1;

BusInterfaceGnd: NAT = 2;

BusInterfacePadGnd: NAT = 3;

BusInterfaceClock: NAT = 4;

BusInterfacenClock: NAT = 5;

BusInterfacenGrant1: NAT = 6;

BusInterfacenGrant2: NAT = 7;

BusInterfaceDataIn: NAT = 8;

BusInterfaceDataOut: NAT = 9;

BusInterfaceToCache: NAT = 10;

BusInterfaceFromCache: NAT = 11;

BusInterfaceIn1: NAT = 12;

BusInterfaceIn2: NAT = 13;

BusInterfaceIn3: NAT = 14;

BusInterfaceOut1: NAT = 15;

BusInterfaceOut2: NAT = 16;

BusInterfaceOut3: NAT = 17;

BusInterfaceTo1: NAT = 18;

BusInterfaceTo2: NAT = 19;

BusInterfaceTo3: NAT = 20;

BusInterfaceFrom1: NAT = 21;

BusInterfaceFrom2: NAT = 22;

BusInterfaceFrom3: NAT = 23;

BusInterfaceState: TYPE = REF BusInterfaceStateRec;

BusInterfaceStateRec: TYPE = RECORD [

lastClock: Ports.Level,

grant1, grant2: Ports.Level];

BusInterface: PUBLIC PROC RETURNS [ct: Core.CellType] = {

p: Core.Wire ← CoreCreate.WireList[LIST["Vdd", "PadVdd", "Gnd", "PadGnd", "Clock", "nClock", "Grant1", "Grant2", CoreCreate.Seq["DataIn", 32], CoreCreate.Seq["DataOut", 32], CoreCreate.Seq["ToCache", 32], CoreCreate.Seq["FromCache", 32], "In1", "In2", "In3", "Out1", "Out2", "Out3", "To1", "To2", "To3", "From1", "From2", "From3"]];

ct ← CoreClasses.CreateUnspecified[name: BusInterfaceName, public: p];

[] ← Ports.InitPort[wire: p[BusInterfaceClock], levelType: l];

[] ← Ports.InitPort[wire: p[BusInterfacenClock], levelType: l];

[] ← Ports.InitPort[wire: p[BusInterfacenGrant1], levelType: l];

[] ← Ports.InitPort[wire: p[BusInterfacenGrant2], levelType: l];

FOR i: NAT IN [0..32) DO

[] ← Ports.InitPort[wire: p[BusInterfaceDataIn][i], levelType: l];

[] ← Ports.InitPort[wire: p[BusInterfaceDataOut][i], levelType: l];

[] ← Ports.InitPort[wire: p[BusInterfaceToCache][i], levelType: l, initDrive: drive];

[] ← Ports.InitPort[wire: p[BusInterfaceFromCache][i], levelType: l];

ENDLOOP;

FOR i: NAT IN [0..3) DO

[] ← Ports.InitPort[wire: p[BusInterfaceIn1+i], levelType: l];

[] ← Ports.InitPort[wire: p[BusInterfaceOut1+i], levelType: l];

[] ← Ports.InitPort[wire: p[BusInterfaceTo1+i], levelType: l, initDrive: drive];

[] ← Ports.InitPort[wire: p[BusInterfaceFrom1+i], levelType: l];

ENDLOOP;

};

BusInterfaceInit: Rosemary.InitProc = {

stateAny ← NEW[BusInterfaceStateRec];

};

BusInterfaceSimple: Rosemary.EvalProc = {

state: BusInterfaceState ← NARROW[stateAny];

IF p[BusInterfaceClock].l=H AND state.lastClock=L THEN {

state.grant1 ← p[BusInterfacenGrant1].l;

state.grant2 ← p[BusInterfacenGrant2].l;

FOR i: NAT IN [0..32) DO

ENDLOOP;

};

state.lastClock ← p[BusInterfaceClock].l;

FOR i: NAT IN [0..32) DO

p[BusInterfaceData][i].l ← L;

p[BusInterfaceData][i].d ← IF state.dataInLatch[i]#H THEN drive ELSE none;

p[BusInterfaceDataOut][i].l ← L;

p[BusInterfaceDataOut][i].d ← IF state.dataOutLatch[i]#H THEN drive ELSE none;

ENDLOOP;

FOR i: NAT IN [0..3) DO

p[BusInterfaceBus1+i].l ← L;

p[BusInterfaceBus1+i].d ← IF state.latchIn[i]#H THEN drive ELSE none;

p[BusInterfaceOut1+i].l ← L;

p[BusInterfaceOut1+i].d ← IF state.latchOut[i]#H THEN drive ELSE none;

ENDLOOP;

};

RosemaryUser.RegisterTestProc["BasicTest", BasicTest];

END.