Internal Memo

XEROX
To    From
June87 Interest    Rick Barth
    PARC-CSL





Subject    Date
June87 Logic Diagrams    July 24, 1986


Introduction
    This document describes the structure of the machine above the responsibility of individual designers.
Issues
Arbitration
    My theory on arbitration is that there is a line which does more or less the same thing as a data line which says no new memory 
    requests.  It is generally only pulled by a memory module when its FIFO might fill up.  No more start packets may be issued 
    while this line is asserted.
    The request/grant lines are statically allocated to the board slots.  4 to io/display, 4 to memory and 8 apiece to the other three 
    slots.  One io/display is lowest priority, one is highest priority, all the others are round robin in between. 
Serial Debug Bus
    What should such a bus look like?  Presumably we are now constrained by what the EU and IFU implement.
Power
    Processor - 40 + Terminators - 15 => 55 /processor board
    Backplane termination => 10
    Memory board => 100
    Disk drive => 25
    I/O board => 35
    Display controller => 20
    Fans => 10
    Basic board set total - 260
    Another processor board => 55
    Another memory board => 100
    Total - 415
    @ 70% power supply efficiency => 600
    Plus 200 watt color monitor.