My theory on arbitration is that there is a line which does more or less the same thing as a data line which says no new memory requests. It is generally only pulled by a memory module when its FIFO might fill up. No more start packets may be issued while this line is asserted.

The request/grant lines are statically allocated to the board slots. 4 to io/display, 4 to memory and 8 apiece to the other three slots. One io/display is lowest priority, one is highest priority, all the others are round robin in between.

What should such a bus look like? Presumably we are now constrained by what the EU and IFU implement.