Without Power and Ground there are 100 wires. The AT bus has 10 Power & Ground lines.
Address Bus
SA19-SA0 (System Address Lines)
These lines are superset of the 20 lines, SA0-SA19, available on the AT I/O bus.
SA0-SA19 are gated onto the bus when BALE is asserted high; latched on the falling edge of BALE.
LA23-LA17 (Local Address Lines)
Valid when BALE is asserted. They are not latched during IO controller cycles and therefore are not valid for the whole cycle. Their purpose is to provide memory decodes for 16-bit, 1-wait state, memory cycles.
Data Bus
SD15-SD8 (System Data Lines)
SD7-SD0 (System Data Lines)
Support for byte-wide devices is provide by having them use SD0-SD7 when communicating with the master and having the controller multiplex the high order byte into the low order byte.
Control Signals
BALE (Buffer Address Latch Enable)
Indicates a valid DMA address when used with AEN. BALE is forced active high during DMA cycles.
MEMCS16 (16-bit Memory Device)
Indicates to the system that the present data transfer is a 16-bit, 1 wait-state, memory cycle.
It must be derived from the decoding of UnbufferedAddrBus. Asserted low.
IOCS16 (16-bit I/O Device)
Indicates to the system that the present data transfer is a 16-bit, 1 wait-state, I/O cycle.
It is derived from a decoding of SloAddressBus. Asserted low.
-IOCHCK (IO Transfer Error Condition)
Provides parity information IO devices. This signal is asserted low and indicates a non-recoverable system error.
IOCHRDY (Input)
Pulled low by IO device to lengthen IO or memory cycle. This signal should not be held low for more than 2.5 microseconds.
AEN (Address Enable)
Used by the DMA device to decouple other IO devices from the DMA channel. When asserted high, the DMA device has control of the AddressBus, DataBus Read/Write command lines.
SBHE (System Byte High Enable)
Indicates transfer of data on the high byte of the SloDataBus. Asserted high.
CLK (System Clock)
The system clock runs at half the frequency of the processor clock.
OSC (Output)
The AT IO bus supplies a 14.32 MHz clock. This clock is not synchronized with the AT system clock.
OWS (Zero Wait State Condition)
This signal informs the 80286 that it can complete the present bus cycle without the insertion of additional wait states. Asserted low.
-MEMW (Memory Write)
Active on all memory write cycles. Driven by any device.
-MEMR (Memory Read)
Active on all memory read cycles. Driven by any device.
-SMEMW (Output)
Derived from -MEMW.
-SMEMR (Output)
Derived from -MEMR.
-IOW (I/O Write)
Instructs the IO device to read data from the SloDataBus. Asserted low.
-IOR (I/O Read)
Instructs the IO device to drive its data onto the SloDataBus. Asserted low.
RESETDRV (System Reset)
Used to reset or initialize the system. Asserted high.
DMA Signals
-DACK (DMA Acknowledge)
Used to acknowledge DMA requests.
DRQ (DMA Request)
Asynchronous channel requests used by IO devices to gain DMA service.
7 DMA channels; DRQ0 has highest priority; DRQ7 has lowest.
TC (Terminal Count )
Used to notify the currently selected peripheral that the present DMA cycle should be the last cycle for this data block.
-MASTER
Used with the ReqDMABus line to gain control of the system.
-REFRESH
Used to indicate a refresh cycle on the ATBus. Asserted low by the IOP controller.