<> <> <> <> DIRECTORY Atom, Cluster2, Convert, Core, CoreFlat, CoreName, Dragon, EU2, EU2Utils, HandCodingUtil, IFU2, IFUPLAInstrDecode, IFUPLAMainPipeControl, IFUTest, IO, REFBit, Rope, Rosemary, RoseTV, TerminalIO; IFUTestUtils: CEDAR PROGRAM IMPORTS Atom, Cluster2, Convert, CoreFlat, CoreName, HandCodingUtil, IO, REFBit, Rope, Rosemary, RoseTV, TerminalIO EXPORTS IFUTest = BEGIN <<>> <<_ &v _ ViewerOps.FindViewer["Interp: World:Local"]>> <<_ ViewerOps.DestroyViewer[&v]>> <<>> <> <<_ &v _ ViewerOps.FindViewer["Interp: World:Local"]>> <<_ &out _ ViewerIO.CreateViewerStreams["Stuffin", &v].out>> <<_ IO.PutRope[&out, "&sgf[IFUTestUtils]"]>> <<>> <> <> <> <> <> <> <> <> <> <> <<&sgf[IFUTestUtils]>> UpdateProc: TYPE = IFUTest.UpdateProc; RTVal: TYPE = RoseTV.RTVal; ROPE: TYPE = Rope.ROPE; II: TYPE = IFU2.II; NextMacro: TYPE = IFUPLAInstrDecode.NextMacro; CondEffect: TYPE = IFUPLAMainPipeControl.CondEffect; CondSelects: TYPE = Dragon.CondSelects; ALULeftSources: TYPE = Dragon.ALULeftSources; ALURightSources: TYPE = Dragon.ALURightSources; Store2ASources: TYPE = Dragon.Store2ASources; ALUOps: TYPE = Dragon.ALUOps; PBusFaults: TYPE = Dragon.PBusFaults; AluOpRp: ARRAY ALUOps OF ROPE = ["Or", "And", "VAd2", "BChk", "SAdd", "SSub", "LAdd", "LSub", "Xor", "?9", "FOP", "?11", "VAdd", "VSub", "UAdd", "USub"]; LtSrcRp: ARRAY ALULeftSources OF ROPE = ["a", "r", "c", "?"]; RtSrcRp: ARRAY ALURightSources OF ROPE = ["b", "r", "c", "k", "f", "?", "?", "?"]; StSrcRp: ARRAY Store2ASources OF ROPE = ["b", "r", "c", "?"]; PhRp: ARRAY Dragon.Phase OF ROPE = ["A", "B"]; BoolRp: ARRAY BOOL OF ROPE = [FALSE: "F", TRUE: "T"]; <> <<["Get", "--?", "-?-", "Jmp", "?--", "Hld", "??-", "???"];>> NextMacroRp: ARRAY [0..8) OF ROPE =["Get", "--?", "-?-", "Jmp", "?--", "Hld", "??-", "???"]; CondEffectRp: ARRAY CondEffect OF ROPE = ["macroT", "macroJ", "microJ", "bubble"]; -- %6g CondSelectRp: ARRAY CondSelects OF ROPE = [ -- %3g "--", "EZ", "LZ", "LE", "?4", "NE", "GE", "GZ", "Ovf", "BC", "IL", "?11", "?12", "nBC", "nIL", "MFt"]; OpCodeRpRef: HandCodingUtil.NameArray _ HandCodingUtil.GetInstArray[]; OpCodeRp: PROC[op: [0..256)] RETURNS [ROPE] = {RETURN[OpCodeRpRef[LOOPHOLE[op]]]}; DPFaultRp: ARRAY [0..16) OF ROPE = [ -- %3g "non", "?1","?2","?3","?4","?5","?6","?7", "mem", "io", "pg", "wt", "au", "?13", "?14", "?15"]; CondRope: PROC[rope: ROPE, cond: BOOL] = {IF cond THEN TerminalIO.WriteRope[rope] ELSE WriteSpace[rope.Length[]] }; WriteSpace: PROC[size: INT] = {THROUGH [0..size) DO TerminalIO.WriteChar[IO.SP] ENDLOOP}; Signal: SIGNAL = CODE; ShowCluster2: PUBLIC PROC = { tos: IO.STREAM _ TerminalIO.TOS[]; TerminalIO.WriteF["%L\n", IO.char['f]]; TerminalIO.WriteRope["TOP\n"]; ShowClusterStates[Cluster2.lastKs.stateTop]; TerminalIO.WriteRope["FULL\n"]; ShowClusterStates[Cluster2.lastKs.stateFull]}; ShowClusterStates: PROC[states: ARRAY [0..Cluster2.historySize) OF Cluster2.ClusterState] ={}; DisplayType: TYPE = {eu, cjump, fetch, xbus, pipe, stack, instr, test}; DisplayTypeRp: ARRAY DisplayType OF ROPE _ ["EU", "CJump", "Fetch", "Xbus", "Pipe", "Stack", "Instr", "Test"]; ShowAll: PUBLIC PROC = { FOR type: DisplayType IN [eu..cjump] DO ShowTop[type] ENDLOOP; FOR type: DisplayType IN [fetch..test] DO Show[type] ENDLOOP}; ShowLast: PUBLIC PROC = { FOR type: DisplayType IN [eu..cjump] DO ShowStates[top, last, type] ENDLOOP; FOR type: DisplayType IN [fetch..test] DO ShowStates[top, last, type]; ShowStates[full, last, type] ENDLOOP}; ShowTop: PUBLIC PROC[type: DisplayType] = { TerminalIO.WriteF["\n%g\n", IO.rope[DisplayTypeRp[type]]]; TerminalIO.WriteRope[" TOP\n"]; ShowStates[top, all, type]}; Show: PUBLIC PROC[type: DisplayType] = { TerminalIO.WriteF["%g\n", IO.rope[DisplayTypeRp[type]]]; TerminalIO.WriteRope[" TOP\n"]; ShowStates[top, all, type]; TerminalIO.WriteRope[" FULL\n"]; ShowStates[full, all, type]}; ShowStates: PROC[which: {top, full}, range: {last, all}, type: DisplayType] = { states: ARRAY [0..Cluster2.historySize) OF Cluster2.ClusterState _ IF which=top THEN Cluster2.lastKs.stateTop ELSE Cluster2.lastKs.stateFull; end: INT _ IF range=last THEN 1 ELSE Cluster2.historySize-1; tos: IO.STREAM _ TerminalIO.TOS[]; tf: ROPE _ IF which=top THEN "T" ELSE "F"; FOR i: INT DECREASING IN [0..end) DO -- state0=state1 ia: IFU2.IFUState _ NARROW[states[i+1 ].data[ifu]]; ib: IFU2.IFUState _ NARROW[states[i ].data[ifu]]; ea: EU2.EU2State _ NARROW[states[i+1 ].data[eu]]; eb: EU2.EU2State _ NARROW[states[i ].data[eu]]; xbus: IFU2.RegAddrRec _ LOOPHOLE[ib.XBus]; IF states[i].refPh^=a THEN LOOP; IF states[i+1].refPh^#a THEN LOOP; IF states[i].refPh^#b THEN LOOP; IF states[i].refCy^#states[i+1].refCy^ THEN LOOP; <> <> tos.PutF["%g%g %3g ", IO.char[DisplayTypeRp[type].Fetch[]], IO.rope[tf], IO.int[states[i].refCy^] ]; SELECT type FROM test => { tos.PutF["A:%02x ", IO.int[ ia.aPipe [1][a] ] ]; tos.PutF["%02x ", IO.int[ ib.aPipe [1][b] ] ]; tos.PutF["B:%02x ", IO.int[ ia.bPipe [1][a] ] ]; tos.PutF["%02x ", IO.int[ ib.bPipe [1][b] ] ]; tos.PutF["C:%02x ", IO.int[ ia.cPipe [1][a] ] ]; tos.PutF["%02x ", IO.int[ ib.cPipe [1][b] ] ]; tos.PutF["%02x ", IO.int[ ia.cPipe [2][a] ] ]; tos.PutF["%02x ", IO.int[ ib.cPipe [2][b] ] ]; tos.PutF["%02x ", IO.int[ ia.cPipe [3][a] ] ]; tos.PutF["%02x ", IO.int[ ib.cPipe [3][b] ] ]; <> <> <> }; pipe => { CondRope[ "Ld1A ", ia.LoadStage1Ac ]; CondRope[ "Ld1B ", ib.LoadStage1Bc ]; CondRope[ "Ld2A ", ia.LoadStage2Ac ]; CondRope[ "(bub) ", ia.Stage2ABubbleBA ]; CondRope[ "Abrt2B ", ib.Stage2BAbortAB ]; CondRope[ "Ld3A ", ia.LoadStage3Ac ]; CondRope[ "(abrt) ", ia.Stage3AAbortBA ]; }; stack => { tos.PutF["%02x ", IO.int[ ib.TosBA ] ]; tos.PutF["%02x ", IO.int[ ib.BosBA ] ]; }; instr => { CondRope[ "* ", ia.ResetBA ]; tos.PutF["%2x ", IO.int[ ia.StateAB ] ]; CondRope[ "Rdy ", ia.InstReadyAB ]; tos.PutF["%5g ", IO.rope[ OpCodeRp[ ia.OpAB ] ] ]; tos.PutF["%2x ", IO.int[ ia.AlphaAB ] ]; tos.PutF["%2x ", IO.int[ ia.BetaAB ] ]; tos.PutF["%2x ", IO.int[ ia.GammaAB ] ]; tos.PutF["%2x ", IO.int[ ia.DeltaAB ] ]; tos.PutF["%g ", IO.rope[ NextMacroRp[ ib.NextMacroBA.ORD ] ] ]; CondRope[ "Rd0 ", ib.DPCmndIsRd0BA ]; CondRope[ "Rd2 ", ib.DPCmndIsRd2BA ]; CondRope[ "ILck ", ib.Stage1BHoldBA ]; tos.PutF["L:%02x ", IO.int[ ib.LBA ] ]; tos.PutF["S:%02x ", IO.int[ ib.SBA ] ]; }; fetch => { CondRope[ "Ftch ", ia.NewFetchBA ]; tos.PutF["a:%08x ", IO.card[ ia.fetchAddrBA ] ]; CondRope[ "Rjt ", ib.IPRejectBA ]; CondRope[ "Flt ", ib.IPFaultingBA ]; CondRope[ "FA ", ia.FetchingAB ]; -- Fix these CondRope[ "FB ", ib.FetchingBA ]; -- Fix these tos.PutF["%02x ", IO.card[ ib.FetchWtAB ] ]; tos.PutF["%02x ", IO.card[ ib.FetchRdBA ] ]; tos.PutF["%02x ", IO.card[ ib.FetchBytesM1AB ] ]; <> <> CondRope[ "IRdy ", ia.InstReadyAB ]; tos.PutF["d:%08x ", IO.card[ ib.IPData ] ]; }; xbus => { tos.PutF["Xa:%08x ", IO.card[ ia.XBus ] ]; tos.PutF["Xb:%08x ", IO.card[ ib.XBus ] ]; tos.PutF["X:%02x ", IO.int[ xbus.aAddr ] ]; tos.PutF["%02x ", IO.int[ xbus.bAddr ] ]; tos.PutF["%02x ", IO.int[ xbus.cAddr ] ]; tos.PutF["l:%g ", IO.rope[ LtSrcRp[ xbus.aluLeftSrc ] ] ]; tos.PutF["r:%g ", IO.rope[ RtSrcRp[ xbus.aluRightSrc ] ] ]; tos.PutF["s:%g ", IO.rope[ StSrcRp[ xbus.storeSrc ] ] ]; CondRope[ "S3C", xbus.st3AisC ]; }; cjump => { tos.PutF["CE2:%6g ", IO.rope[ CondEffectRp[ ia.CondEffect2AB ] ] ]; tos.PutF["CS2:%3g ", IO.rope[ CondSelectRp[ ia.ctlPipe2AB.condSel ] ] ]; CondRope[ "Cond ", ia.EUCondition2BA ]; }; eu => { tos.PutF["%4g ", IO.rope[ AluOpRp[ ib.ctlPipe2AB.aluOp ] ] ]; tos.PutF["2:%3g ", IO.rope[ CondSelectRp[ ib.ctlPipe2AB.condSel ] ] ]; CondRope[ "Cnd ", ib.EUCondition2BA ]; tos.PutF["3:%3g ", IO.rope[ CondSelectRp[ ib.ctlPipe3AB.condSel ] ] ]; CondRope[ "Rd", ib.ctlPipe3AB.rdFromPBus ]; CondRope[ "Wt", ib.ctlPipe3AB.writeToPBus ]; tos.PutF["%08x ", IO.card[ ea.simRegs[EU2Utils.left]]]; tos.PutF["%08x ", IO.card[ ea.simRegs[EU2Utils.right]]]; tos.PutF["%08x ", IO.card[ eb.simRegs[EU2Utils.r2B]]]; CondRope[ "CAB ", ea.carryAB ]; CondRope[ "CBA ", eb.carryBA ]; CondRope[ "Rjt ", ib.DPRejectBA ]; tos.PutF["%3g ", IO.rope[ DPFaultRp[ ib.DPFaultBA.ORD ] ] ]; }; ENDCASE => ERROR; TerminalIO.WriteLn[] ENDLOOP}; <<>> Strip: PROC[path: ROPE _ NIL] RETURNS[ROPE] = { start: INT; WHILE (start_path.Find["("]) # -1 DO path _ Rope.Cat[path.Substr[0,start], path.Substr[path.Index[0, ")"]]] ENDLOOP; RETURN[path]}; Cell: PROC[a,b: ROPE _ NIL] RETURNS[cell: Core.CellType] = { RETURN[IF a.Length[]=0 THEN Cluster2.lastKs.ifuSimulation.cellType ELSE CoreFlat.ResolveFlatCellType [Cluster2.lastKs.ifuSimulation.cellType, FlatCellRec[a,b]].cellType]}; State: PROC[a,b: ROPE _ NIL] RETURNS[ref: REF] = { ref _ Rosemary.GetState [Cluster2.lastKs.ifuSimulation, NEW[CoreFlat.FlatCellTypeRec _ FlatCellRec[a,b]]]}; FlatCellRec: PROC[a,b: ROPE _ NIL] RETURNS[flatCell: CoreFlat.FlatCellTypeRec] = { flatCell _ CoreFlat.ParseCellTypePath[Cluster2.lastKs.ifuSimulation.cellType, Rope.Cat[a,b]]}; PrintWire: PROC[wire: Core.Wire] = { FinishOld: PROC = {nxtOld.idx _ 0; TerminalIO.WriteF["..%g)\n", IO.int[nxtIdx]]}; delayd: BOOL _ FALSE; nxtOld: CoreName.SigRec; nxtIdx: INT _ 0; FOR i: INT IN [0..wire.size) DO name: ROPE _ CoreName.WireNm[wire[i]].n; IF delayd THEN { test: CoreName.SigRec _ CoreName.NameSig[name]; nxtOld.idx _ test.idx; IF nxtOld=test THEN { IF nxtIdx#test.idx THEN TerminalIO.WriteF["..%g) [%g", IO.int[nxtIdx], IO.int[test.idx]]; nxtIdx _ test.idx+1; LOOP}; FinishOld[]}; TerminalIO.WriteF[" %g", IO.rope[name]]; nxtOld _ CoreName.NameSig[name]; IF nxtOld.idx#-1 THEN {delayd _ TRUE; nxtIdx_nxtOld.idx+1} ELSE {delayd _ FALSE; TerminalIO.WriteF["\n"]}; ENDLOOP; IF delayd THEN FinishOld[]}; InitStates: PUBLIC PROC[sim: Rosemary.Simulation, size: CARDINAL] RETURNS[states: IFUTest.StateSeq] = { states _ NEW[IFUTest.StateSeqRec[size]]; FOR i: NAT IN [0..states.size) DO states[i] _ NEW[IFU2.IFUStateRec]; ENDLOOP}; UpdateStates: PUBLIC PROC[ sim: Rosemary.Simulation, states: IFUTest.StateSeq, pass: INT, qph: IFU2.QPh ] = { temp: IFU2.IFUState _ states[states.size-1]; FOR i: NAT DECREASING IN [1..states.size) DO states[i] _ states[i-1] ENDLOOP; states[0] _ temp; UpdateState[sim, states[0], pass, qph]}; heart, lcc, left, dcm, right, rcc: ROPE; fetchIndex, fetchControl, ltDrPadIO, stackControl, mainPipeBdy, mainPipeInDr, mainPipeOutDr, interlock, interlockBdy, stackIndex: ROPE; fetch, fetchBuf, xaForm, pcTop, pcBot, stackBuf, lsForm, abForm, cpipe: ROPE; instrDecode, rtDrPadIO, idInDr, idOutDr: ROPE; idBdy0, idBdy1, idBdy2, idBdy3, idBdy4, idBdy5, idBdy6: ROPE; cachedXFers: LIST OF RTVal _ NIL; GetXFers: PROC RETURNS[xfers: LIST OF RTVal] = { IF cachedXFers#NIL THEN RETURN[cachedXFers]; heart _ IF Cluster2.quickIFU THEN "/0" ELSE "/0/2/1/1/1"; lcc _ IF Cluster2.quickIFU THEN "/9" ELSE Rope.Cat[heart, "/0/1"]; left _ IF Cluster2.quickIFU THEN "" ELSE Rope.Cat[heart, "/1"]; dcm _ IF Cluster2.quickIFU THEN "" ELSE Rope.Cat[heart, "/2/1/1"]; right _ IF Cluster2.quickIFU THEN "" ELSE Rope.Cat[heart, "/3"]; rcc _ IF Cluster2.quickIFU THEN "/10" ELSE Rope.Cat[heart, "/4/1"]; fetchIndex _ Rope.Cat[lcc, "/8"]; fetchControl _ Rope.Cat[lcc, "/6"]; ltDrPadIO _ Rope.Cat[lcc, "/5"]; stackControl _ Rope.Cat[lcc, "/4"]; mainPipeBdy _ Rope.Cat[lcc, "/3/1/1/0"]; mainPipeInDr _ Rope.Cat[lcc, "/3/1/0/1"]; mainPipeOutDr _ Rope.Cat[lcc, "/3/1/1/1"]; interlock _ Rope.Cat[lcc, "/2"]; interlockBdy _ Rope.Cat[lcc, "/2/1/1/0"]; stackIndex _ Rope.Cat[lcc, "/0"]; fetch _ Rope.Cat[dcm, "/8"]; fetchBuf _ Rope.Cat[dcm, "/7"]; xaForm _ Rope.Cat[dcm, "/6"]; pcTop _ Rope.Cat[dcm, "/5"]; pcBot _ Rope.Cat[dcm, "/4"]; stackBuf _ Rope.Cat[dcm, "/3"]; lsForm _ Rope.Cat[dcm, "/2"]; abForm _ Rope.Cat[dcm, "/1"]; cpipe _ Rope.Cat[dcm, "/0"]; instrDecode _ Rope.Cat[rcc, "/2"]; rtDrPadIO _ Rope.Cat[rcc, "/1"]; idInDr _ Rope.Cat[instrDecode, "/1/1/1"]; idOutDr _ Rope.Cat[instrDecode, "/1/0"]; idBdy0 _ Rope.Cat[idOutDr, "/0/0"]; idBdy1 _ Rope.Cat[idOutDr, "/1/0"]; idBdy2 _ Rope.Cat[idOutDr, "/2/0"]; idBdy3 _ Rope.Cat[idOutDr, "/3/0"]; idBdy4 _ Rope.Cat[idOutDr, "/4/0"]; idBdy5 _ Rope.Cat[idOutDr, "/5/0"]; idBdy6 _ Rope.Cat[idOutDr, "/6/0"]; cachedXFers _ xfers _ LIST[ RoseTV.New[right, "StateAB", StateAB, FALSE, FBN], RoseTV.New[right, "InstReadyAB", InstReadyAB, FALSE, FBN], RoseTV.New[right, "OpAB", OpAB, FALSE, FBN], RoseTV.New[xaForm, "AlphaAB", AlphaAB, FALSE, FBN], RoseTV.New[xaForm, "BetaAB", BetaAB, FALSE, FBN], RoseTV.New[xaForm, "GammaAB", GammaAB, FALSE, FBN], RoseTV.New[xaForm, "DeltaAB", DeltaAB, FALSE, FBN], RoseTV.New[heart, "TosBA", TosBA, FALSE, FBN], RoseTV.New[heart, "BosBA", BosBA, FALSE, FBN], RoseTV.New[lsForm, "LBA", LBA, FALSE, FBN], RoseTV.New[lsForm, "SBA", SBA, FALSE, FBN], RoseTV.New[right, "NextMacroBA", NextMacroBA, FALSE, FBN], RoseTV.New[right, "DPCmndIsRd0BA", DPCmndIsRd0BA, FALSE, FBN], RoseTV.New[left, "DPCmndIsRd2BA", DPCmndIsRd2BA, FALSE, FBN], RoseTV.New[left, "Stage1BHoldBA", Stage1BHoldBA, FALSE, FBN], RoseTV.New[left, "LoadStage1Ac", LoadStage1Ac, FALSE, FBN], RoseTV.New[left, "LoadStage1Bc", LoadStage1Bc, FALSE, FBN], RoseTV.New[left, "LoadStage2Ac", LoadStage2Ac, FALSE, FBN], RoseTV.New[left, "Stage2BAbortAB", Stage2BAbortAB, FALSE, FBN], RoseTV.New[left, "LoadStage3Ac", LoadStage3Ac, FALSE, FBN], RoseTV.New[left, "Stage3AAbortBA", Stage3AAbortBA, FALSE, FBN], RoseTV.New[left, "CondEffect2BA", CondEffect2BA, FALSE, FBN], RoseTV.New[left, "NewFetchBA", NewFetchBA, FALSE, FBN], RoseTV.New[fetch, "FetchAddrBA", FetchAddrBA, FALSE, FBN], RoseTV.New[heart, "IPData", IPData, FALSE, FBN], RoseTV.New[left, "FetchWtAB", FetchWtAB, FALSE, FBN], RoseTV.New[left, "FetchRdBA", FetchRdBA, FALSE, FBN], RoseTV.New[left, "FetchBytesM1AB", FetchBytesM1AB, FALSE, FBN], RoseTV.New[dcm, "XBus", XBus, FALSE, FBN], RoseTV.New[right, "DPFaultBA", DPFaultBA, FALSE, FBN], RoseTV.New[right, "DPRejectBA", DPRejectBA, FALSE, FBN], RoseTV.New[left, "IPRejectBA", IPRejectBA, FALSE, FBN], RoseTV.New[left, "IPFaultingBA", IPFaultingBA, FALSE, FBN], RoseTV.New[left, "FetchingBA", FetchingBA, FALSE, FBN], RoseTV.New[cpipe, "EUAluOp1AB", AluOp1AB, FALSE, FBN], RoseTV.New[cpipe, "EUAluOp1BA", AluOp1BA, FALSE, FBN], RoseTV.New[cpipe, "EUAluOp2AB", AluOp2AB, FALSE, FBN], RoseTV.New[abForm, "A1AB", A1AB, FALSE, FBN], RoseTV.New[abForm, "A1BA", A1BA, FALSE, FBN], RoseTV.New[abForm, "B1AB", B1AB, FALSE, FBN], RoseTV.New[abForm, "B1BA", B1BA, FALSE, FBN], RoseTV.New[lsForm, "C1AB", C1AB, FALSE, FBN], RoseTV.New[lsForm, "C1BA", C1BA, FALSE, FBN], RoseTV.New[lsForm, "C2AB", C2AB, FALSE, FBN], RoseTV.New[lsForm, "C2BA", C2BA, FALSE, FBN], RoseTV.New[lsForm, "C3AB", C3AB, FALSE, FBN], RoseTV.New[lsForm, "C3BA", C3BA, FALSE, FBN], RoseTV.New[left, "ResetBA", ResetBA, FALSE, FBN]]}; <<>> <> UpdateState: PUBLIC UpdateProc = { RoseTV.XFerList[sim, GetXFers[]]; state.cycle _ pass; state.ph _ qph; state.StateAB _ StateAB^; state.InstReadyAB _ InstReadyAB^; state.OpAB _ OpAB^; state.AlphaAB _ AlphaAB^; state.BetaAB _ BetaAB^; state.GammaAB _ GammaAB^; state.DeltaAB _ DeltaAB^; state.TosBA _ TosBA^; state.BosBA _ BosBA^; state.LBA _ LBA^; state.SBA _ SBA^; state.NextMacroBA _ NextMacroBA^; state.DPCmndIsRd0BA _ DPCmndIsRd0BA^; state.DPCmndIsRd2BA _ DPCmndIsRd2BA^; state.Stage1BHoldBA _ Stage1BHoldBA^; state.LoadStage1Ac _ LoadStage1Ac^; state.LoadStage1Bc _ LoadStage1Bc^; state.LoadStage2Ac _ LoadStage2Ac^; state.Stage2BAbortAB _ Stage2BAbortAB^; state.LoadStage3Ac _ LoadStage3Ac^; state.Stage3AAbortBA _ Stage3AAbortBA^; state.CondEffect2BA _ CondEffect2BA^; state.NewFetchBA _ NewFetchBA^; state.fetchAddrBA _ FetchAddrBA^; state.IPData _ IPData^; state.FetchWtAB _ FetchWtAB^; state.FetchRdBA _ FetchRdBA^; state.FetchBytesM1AB _ FetchBytesM1AB^; state.XBus _ XBus^; state.DPFaultBA _ DPFaultBA^; state.DPRejectBA _ DPRejectBA^; state.IPRejectBA _ IPRejectBA^; state.IPFaultingBA _ IPFaultingBA^; state.FetchingBA _ FetchingBA^; state.ctlPipe1AB.aluOp _ AluOp1AB^; state.ctlPipe1BA.aluOp _ AluOp1BA^; state.ctlPipe2AB.aluOp _ AluOp2AB^; state.aPipe[1][a] _ A1AB^; state.aPipe[1][b] _ A1BA^; state.bPipe[1][a] _ B1AB^; state.bPipe[1][b] _ B1BA^; state.cPipe[1][a] _ C1AB^; state.cPipe[1][b] _ C1BA^; state.cPipe[2][a] _ C2AB^; state.cPipe[2][b] _ C2BA^; state.cPipe[3][a] _ C3AB^; state.cPipe[3][b] _ C3BA^; state.ResetBA _ ResetBA^; IF state.ph = B THEN ShowLast[]}; StateAB: REF Dragon.HexByte _ NEW[Dragon.HexByte]; InstReadyAB: REF RoseTV.Bool _ NEW[RoseTV.Bool]; OpAB: REF Dragon.HexByte _ NEW[Dragon.HexByte]; AlphaAB: REF Dragon.HexByte _ NEW[Dragon.HexByte]; BetaAB: REF Dragon.HexByte _ NEW[Dragon.HexByte]; GammaAB: REF Dragon.HexByte _ NEW[Dragon.HexByte]; DeltaAB: REF Dragon.HexByte _ NEW[Dragon.HexByte]; TosBA: REF [0..32) _ NEW[[0..32)]; BosBA: REF [0..32) _ NEW[[0..32)]; LBA: REF Dragon.HexByte _ NEW[Dragon.HexByte]; SBA: REF Dragon.HexByte _ NEW[Dragon.HexByte]; NextMacroBA: REF NextMacro _ NEW[NextMacro]; DPCmndIsRd0BA: REF RoseTV.Bool _ NEW[RoseTV.Bool]; DPCmndIsRd2BA: REF RoseTV.Bool _ NEW[RoseTV.Bool]; Stage1BHoldBA: REF RoseTV.Bool _ NEW[RoseTV.Bool]; LoadStage1Ac: REF RoseTV.Bool _ NEW[RoseTV.Bool]; LoadStage1Bc: REF RoseTV.Bool _ NEW[RoseTV.Bool]; LoadStage2Ac: REF RoseTV.Bool _ NEW[RoseTV.Bool]; Stage2BAbortAB: REF RoseTV.Bool _ NEW[RoseTV.Bool]; LoadStage3Ac: REF RoseTV.Bool _ NEW[RoseTV.Bool]; Stage3AAbortBA: REF RoseTV.Bool _ NEW[RoseTV.Bool]; CondEffect2BA: REF CondEffect _ NEW[CondEffect]; NewFetchBA: REF RoseTV.Bool _ NEW[RoseTV.Bool]; FetchAddrBA: REF RoseTV.LongCard _ NEW[RoseTV.LongCard]; IPData: REF RoseTV.LongCard _ NEW[RoseTV.LongCard]; FetchWtAB: REF [0..4) _ NEW[[0..4)]; FetchRdBA: REF [0..16) _ NEW[[0..16)]; FetchBytesM1AB: REF [0..32) _ NEW[[0..32)]; XBus: REF RoseTV.LongCard _ NEW[RoseTV.LongCard]; DPFaultBA: REF PBusFaults _ NEW[PBusFaults]; DPRejectBA: REF RoseTV.Bool _ NEW[RoseTV.Bool]; IPRejectBA: REF RoseTV.Bool _ NEW[RoseTV.Bool]; IPFaultingBA: REF RoseTV.Bool _ NEW[RoseTV.Bool]; FetchingBA: REF RoseTV.Bool _ NEW[RoseTV.Bool]; AluOp1AB: REF ALUOps _ NEW[ALUOps]; AluOp1BA: REF ALUOps _ NEW[ALUOps]; AluOp2AB: REF ALUOps _ NEW[ALUOps]; A1AB: REF Dragon.HexByte _ NEW[Dragon.HexByte]; A1BA: REF Dragon.HexByte _ NEW[Dragon.HexByte]; B1AB: REF Dragon.HexByte _ NEW[Dragon.HexByte]; B1BA: REF Dragon.HexByte _ NEW[Dragon.HexByte]; C1AB: REF Dragon.HexByte _ NEW[Dragon.HexByte]; C1BA: REF Dragon.HexByte _ NEW[Dragon.HexByte]; C2AB: REF Dragon.HexByte _ NEW[Dragon.HexByte]; C2BA: REF Dragon.HexByte _ NEW[Dragon.HexByte]; C3AB: REF Dragon.HexByte _ NEW[Dragon.HexByte]; C3BA: REF Dragon.HexByte _ NEW[Dragon.HexByte]; ResetBA: REF RoseTV.Bool _ NEW[RoseTV.Bool]; FBN, FieldBitName: RoseTV.FldBitNmProc = { -- only called for multibit unstructured fields <> SELECT rtv.wwrSize FROM 1 => RETURN[rtv.field]; 32 => RETURN[IO.PutFR["%g.%02b", IO.rope[rtv.field], IO.int[index]] ]; ENDCASE => { bf: REFBit.Format _ REFBit.Desc[rtv.ref].bitForm; sigRec: CoreName.SigRec _ CoreName.NameSig[rtv.field]; name: ROPE _ bf[index].name; IF name.Length[]=0 THEN {name _ bf[index].nameInv; rtv[index].inverted _ NOT rtv[index].inverted}; name _ CoreName.BitRopeToSigRope[name]; sigRec.root _ sigRec.root.Cat[CoreName.RootExt[name].root]; IF CoreName.RootExt[name].ext.Length[]#0 THEN { int: INT _ Convert.IntFromRope[CoreName.RootExt[name].ext.Substr[1]]; IF int#index THEN Signal[]; sigRec.idx _ int}; RETURN[CoreName.SigName[sigRec]]} }; <> <<{RETURN[IF sm IN ['a..'z] THEN sm + LOOPHOLE['A - 'a] ELSE sm]};>> <> <<{RETURN[IO.PutFR["%g%g%g",>> <> <> <> ifuUpdateProc: PUBLIC ATOM _ $IFUUpdateProc; Atom.PutProp[ifuUpdateProc, ifuUpdateProc, NEW[UpdateProc _ UpdateState]]; TerminalIO.WriteF["%L\n%g\n", IO.char['f], IO.time[]]; END.