IFUTestComplete:
CEDAR
PROGRAM
IMPORTS CoreFlat, CoreOps, IFUPublic, IFUSim, IO, PLASim, Ports, Rope, Rosemary, RosemaryUser, IFUTest, TerminalIO
EXPORTS IFUTest =
BEGIN
ROPE: TYPE = Core.ROPE;
CellType: TYPE = Core.CellType;
Wire: TYPE = Core.Wire;
StateSeq: TYPE = IFUTest.StateSeq;
QPh: TYPE = IFUTop.QPh;
QPhRope: ARRAY QPh OF ROPE ← [A: "A", ab: "ab", B: "B", ba: "ba"];
Signal: SIGNAL = CODE;
II: TYPE = IFUPublic.II;
PortData: TYPE = RECORD [ name: ROPE, width: NAT ← 1, drive: Ports.Drive ← none ];
Formality:
PUBLIC
PROC = {
states: StateSeq;
simulation: Rosemary.Simulation;
p: Ports.Port;
display: RosemaryUser.RoseDisplay;
formalTest: ROPE ← "FormalTest";
public: Core.Wire ← IFUPublic.IfuInitializedPublic[];
cell: CellType;
F: BOOL ← FALSE;
cuts: CoreFlat.CutSet ← CoreFlat.CreateCutSet[labels: LIST ["SimplePLA", "UpOneLevel"]];
cell ← IFUSim.FormalIFU[public, TRUE, FALSE];
p ← Ports.CreatePort[cell, TRUE];
simulation ← Rosemary.Instantiate[cell, p, cuts];
display ← RosemaryUser.DisplayViewer
[simulation, cell, formalTest, RosemaryUser.DisplayPortLeafWires[cell]];
RosemaryUser.InitializeDeltas[display];
states ← IFUTest.InitStates[simulation, 8];
p[ II[ KBus ].ORD ].lc ← 0;
p[ II[ EUAluOp ].ORD ].c ← 0;
p[ II[ EUCondSel ].ORD ].c ← 0;
p[ II[ EUCondition ].ORD ].b ← F;
p[ II[ EURdFromPBus ].ORD ].b ← F;
p[ II[ EUWriteToPBus ].ORD ].b ← F;
p[ II[ UserMode ].ORD ].b ← F;
p[ II[ DPCmd ].ORD ].c ← 0;
p[ II[ DPReject ].ORD ].b ← F;
p[ II[ DPFault ].ORD ].c ← 0;
p[ II[ IPData ].ORD ].b ← F;
p[ II[ IPCmdFetch ].ORD ].b ← F;
p[ II[ IPReject ].ORD ].b ← F;
p[ II[ IPFaulting ].ORD ].b ← F;
p[ II[ DShA ].ORD ].b ← F;
p[ II[ DShB ].ORD ].b ← F;
p[ II[ DShRd ].ORD ].b ← F;
p[ II[ DShWt ].ORD ].b ← F;
p[ II[ DShIn ].ORD ].b ← F;
p[ II[ DShOut ].ORD ].b ← F;
p[ II[ Reset ].ORD ].b ← TRUE;
p[ II[ Reschedule ].ORD ].b ← F;
p[ II[ PhA ].ORD ].b ← F;
p[ II[ PhB ].ORD ].b ← F;
FOR pass:
INT
IN [0..10)
DO
DoPass[pass, states, p, display];
IFUTest.ShowComplete[states] ENDLOOP;
Signal[]};
DoPass:
PROC [pass:
INT, states: StateSeq, p: Ports.Port, display: RosemaryUser.RoseDisplay] =
{FOR ph: QPh IN QPh DO DoQPh[ph, pass, states, p, display] ENDLOOP};
DoQPh:
PROC
[ph: QPh, pass: INT, states: StateSeq, p: Ports.Port, display: RosemaryUser.RoseDisplay] = {
time: INT ← 4*pass + (SELECT ph FROM A => 0, ab => 1, B => 2, ba => 3, ENDCASE => ERROR);
p[ II[ PhA ].ORD ].b ← ph = A;
p[ II[ PhB ].ORD ].b ← ph = B;
TerminalIO.PutF["Pass %g %g %g\n",
IO.int[pass], IO.rope[QPhRope[ph]], IO.time[]];
RosemaryUser.LogSettle[display, time !
Rosemary.Stop => {
flatWire: CoreFlat.FlatWire ← NARROW[data];
name: ROPE ← CoreOps.GetShortWireName[flatWire.wire];
IF name.Length[]>0
THEN TerminalIO.PutF["%g = X\n", IO.rope[name]]
ELSE TerminalIO.PutRope["?????????? = X\n"]; RESUME}];
SELECT ph FROM A,B => IFUTest.UpdateStates[display.simulation, states, pass, ph]; ENDCASE;
RosemaryUser.UpdateDisplay[display];
IF PLASim.BadIns[] THEN TerminalIO.PutRope["BadIns"]};
RosemaryUser.RegisterTestProc[formalTest, FormalTest];
simulation ← RosemaryUser.TestProcedureViewer[
cellType: cell,
testButtons: LIST[formalTest],
name: formalTest,
displayWires: RosemaryUser.DisplayCellTypePortLeafWires[cell],
flatten: TRUE,
cutSets: cuts]};
FormalTest: RosemaryUser.TestProc = {
T: BOOL = TRUE; F: BOOL = FALSE;
p[ II[ KBus ].ORD ].lc ← 0;
p[ II[ EUAluOp ].ORD ].c ← 0;
p[ II[ EUCondSel ].ORD ].c ← 0;
p[ II[ EUCondition ].ORD ].b ← F;
p[ II[ EURdFromPBus ].ORD ].b ← F;
p[ II[ EUWriteToPBus ].ORD ].b ← F;
p[ II[ UserMode ].ORD ].b ← F;
p[ II[ DPCmd ].ORD ].c ← 0;
p[ II[ DPReject ].ORD ].b ← F;
p[ II[ DPFault ].ORD ].c ← 0;
p[ II[ IPData ].ORD ].b ← F;
p[ II[ IPCmdFetch ].ORD ].b ← F;
p[ II[ IPReject ].ORD ].b ← F;
p[ II[ IPFaulting ].ORD ].b ← F;
p[ II[ DShA ].ORD ].b ← F;
p[ II[ DShB ].ORD ].b ← F;
p[ II[ DShRd ].ORD ].b ← F;
p[ II[ DShWt ].ORD ].b ← F;
p[ II[ DShIn ].ORD ].b ← F;
p[ II[ DShOut ].ORD ].b ← F;
p[ II[ Reset ].ORD ].b ← TRUE;
p[ II[ Reschedule ].ORD ].b ← F;
p[ II[ PhA ].ORD ].b ← TRUE;
p[ II[ PhB ].ORD ].b ← F;
Eval[];
Signal[] -- Whew! -- };
END.