<> <> <> <<>> DIRECTORY Core, CoreClasses, CoreLibrary, CoreName, CoreOps, CoreWire, Ports, Rosemary; IFUTest: CEDAR PROGRAM IMPORTS CoreClasses, CoreLibrary, CoreName, CoreOps, CoreWire, Ports, Rosemary = BEGIN ROPE: TYPE = Core.ROPE; Signal: SIGNAL = CODE; TestVectors: TYPE = REF TestVectorSeq; TestVectorSeq: TYPE = RECORD[SEQUENCE size: CARDINAL OF TestRec]; TestRec: TYPE = RECORD[c0, c1, i0, i1, out: Ports.Level _ X]; GeneralPurposeTest: PROC[name: ROPE, vectors: TestVectors] = { cell: Core.CellType _ Extract[name]; Simulate[cell, vectors]}; Extract: PROC[name: ROPE] RETURNS[cell: Core.CellType]={ cell _ CoreLibrary.Get[library, name]; <> <> <<$PWCoreLayout, $SinixCMosBInstance, $SinixCMosBWireGeometry];>> <> }; Simulate: PROC[cell: Core.CellType, vectors: TestVectors] = { DoSim: PROC[index: CARDINAL] = { v: TestRec _ vectors[index]; IF (v.c0=X) # (ctl0=-1) THEN Signal[]; IF (v.c1=X) # (ctl1=-1) THEN Signal[]; IF (v.i0=X) # (in0=-1) THEN Signal[]; IF (v.i1=X) # (in1=-1) THEN Signal[]; IF v.c0#X THEN testerPort[ctl0].l _ v.c0; IF v.c1#X THEN testerPort[ctl1].l _ v.c1; IF v.i0#X THEN testerPort[in0].l _ v.i0; IF v.i1#X THEN testerPort[in1].l _ v.i1; Rosemary.Settle[simulation]; IF testerPort[out].l#v.out THEN Signal[]}; ctl0, ctl1, in0, in1, out, VDD, GND: INT; testerWire: CoreWire.CWire; testerPort: Ports.Port; simulation: Rosemary.Simulation; testerWire _ [cell.public]; ctl0 _ CoreOps.GetWireIndex[testerWire.w, "0"]; ctl1 _ CoreOps.GetWireIndex[testerWire.w, "1"]; in0 _ CoreOps.GetWireIndex[testerWire.w, "in0"]; in1 _ CoreOps.GetWireIndex[testerWire.w, "in1"]; out _ CoreOps.GetWireIndex[testerWire.w, "out0"]; VDD _ CoreOps.GetWireIndex[testerWire.w, "VDD"]; GND _ CoreOps.GetWireIndex[testerWire.w, "GND"]; IF ctl0#-1 THEN []_Ports.InitPort[wire: testerWire.i[ctl0].w, initType: l, initDrive: force]; IF ctl1#-1 THEN []_Ports.InitPort[wire: testerWire.i[ctl1].w, initType: l, initDrive: force]; IF in0#-1 THEN []_Ports.InitPort[wire: testerWire.i[in0].w, initType: l, initDrive: force]; IF in1#-1 THEN []_Ports.InitPort[wire: testerWire.i[in1].w, initType: l, initDrive: force]; []_Ports.InitPort[wire: testerWire.i[out].w, initType: l, initDrive: none]; IF ctl0#-1 THEN []_Ports.InitTesterDrive[wire: testerWire.i[ctl0].w, initDrive: force]; IF ctl1#-1 THEN []_Ports.InitTesterDrive[wire: testerWire.i[ctl1].w, initDrive: force]; IF in0#-1 THEN []_Ports.InitTesterDrive[wire: testerWire.i[in0].w, initDrive: force]; IF in1#-1 THEN []_Ports.InitTesterDrive[wire: testerWire.i[in1].w, initDrive: force]; []_Ports.InitTesterDrive[wire: testerWire.i[out].w, initDrive: none]; [ ] _ Rosemary.SetFixedWire[testerWire.w[VDD], H]; [ ] _ Rosemary.SetFixedWire[testerWire.w[GND], L]; testerPort _ Ports.CreatePort[testerWire.w, TRUE]; simulation _ Rosemary.InstantiateInstances[cell, testerPort]; FOR index1: CARDINAL IN [0..vectors.size) DO DoSim[index1]; ENDLOOP }; TestSAdder: PROC = { DoSim: PROC[index: CARDINAL] = { carry: BOOL _ ((index/1) MOD 2) = 1; ain: BOOL _ ((index/2) MOD 2) = 1; bin: BOOL _ ((index/4) MOD 2) = 1; testerPort[cyI].l _ IF carry THEN H ELSE L; testerPort[in0].l _ IF ain THEN H ELSE L; testerPort[in1].l _ IF bin THEN H ELSE L; Rosemary.Settle[simulation]; IF (carry#ain)#(bin#(testerPort[out].l=H)) THEN Signal[]; IF (carry AND (ain OR bin) OR ain AND bin)#(testerPort[cyO].l=H) THEN Signal[]}; cyI, cyO, in0, in1, out, VDD, GND: INT; testerWire: CoreWire.CWire; testerPort: Ports.Port; simulation: Rosemary.Simulation; cell: Core.CellType _ Extract["DpAdderSerial"]; testerWire _ [cell.public]; cyI _ CoreOps.GetWireIndex[testerWire.w, "rt0"]; cyO _ CoreOps.GetWireIndex[testerWire.w, "0"]; in0 _ CoreOps.GetWireIndex[testerWire.w, "in0"]; in1 _ CoreOps.GetWireIndex[testerWire.w, "in1"]; out _ CoreOps.GetWireIndex[testerWire.w, "out0"]; VDD _ CoreOps.GetWireIndex[testerWire.w, "VDD"]; GND _ CoreOps.GetWireIndex[testerWire.w, "GND"]; []_Ports.InitPort[wire: testerWire.i[cyI].w, initType: l, initDrive: force]; []_Ports.InitPort[wire: testerWire.i[cyO].w, initType: l, initDrive: none]; []_Ports.InitPort[wire: testerWire.i[in0].w, initType: l, initDrive: force]; []_Ports.InitPort[wire: testerWire.i[in1].w, initType: l, initDrive: force]; []_Ports.InitPort[wire: testerWire.i[out].w, initType: l, initDrive: none]; []_Ports.InitTesterDrive[wire: testerWire.i[cyI].w, initDrive: force]; []_Ports.InitTesterDrive[wire: testerWire.i[cyO].w, initDrive: none]; []_Ports.InitTesterDrive[wire: testerWire.i[in0].w, initDrive: force]; []_Ports.InitTesterDrive[wire: testerWire.i[in1].w, initDrive: force]; []_Ports.InitTesterDrive[wire: testerWire.i[out].w, initDrive: none]; [ ] _ Rosemary.SetFixedWire[testerWire.w[VDD], H]; [ ] _ Rosemary.SetFixedWire[testerWire.w[GND], L]; testerPort _ Ports.CreatePort[testerWire.w, TRUE]; simulation _ Rosemary.InstantiateInstances[cell, testerPort]; FOR index1: CARDINAL IN [0..8) DO FOR index2: CARDINAL IN [0..8) DO -- check for hidden state DoSim[index1]; DoSim[index2]; ENDLOOP; ENDLOOP }; TestAllSimples: PROC = { bufVectors: TestVectors _ NEW[TestVectorSeq[2]]; invVectors: TestVectors _ NEW[TestVectorSeq[2]]; orVectors: TestVectors _ NEW[TestVectorSeq[4]]; norVectors: TestVectors _ NEW[TestVectorSeq[4]]; andVectors: TestVectors _ NEW[TestVectorSeq[4]]; nandVectors: TestVectors _ NEW[TestVectorSeq[4]]; xorVectors: TestVectors _ NEW[TestVectorSeq[4]]; xnorVectors: TestVectors _ NEW[TestVectorSeq[4]]; <> bufVectors[0] _ [i0: L, i1: X, out: L]; bufVectors[1] _ [i0: H, i1: X, out: H]; invVectors[0] _ [i0: L, i1: X, out: H]; invVectors[1] _ [i0: H, i1: X, out: L]; orVectors[0] _ [i0: L, i1: L, out: L]; orVectors[1] _ [i0: L, i1: H, out: H]; orVectors[2] _ [i0: H, i1: L, out: H]; orVectors[3] _ [i0: H, i1: H, out: H]; norVectors[0] _ [i0: L, i1: L, out: H]; norVectors[1] _ [i0: L, i1: H, out: L]; norVectors[2] _ [i0: H, i1: L, out: L]; norVectors[3] _ [i0: H, i1: H, out: L]; andVectors[0] _ [i0: L, i1: L, out: L]; andVectors[1] _ [i0: L, i1: H, out: L]; andVectors[2] _ [i0: H, i1: L, out: L]; andVectors[3] _ [i0: H, i1: H, out: H]; nandVectors[0] _ [i0: L, i1: L, out: H]; nandVectors[1] _ [i0: L, i1: H, out: H]; nandVectors[2] _ [i0: H, i1: L, out: H]; nandVectors[3] _ [i0: H, i1: H, out: L]; xorVectors[0] _ [i0: L, i1: L, out: L]; xorVectors[1] _ [i0: L, i1: H, out: H]; xorVectors[2] _ [i0: H, i1: L, out: H]; xorVectors[3] _ [i0: H, i1: H, out: L]; xnorVectors[0] _ [i0: L, i1: L, out: H]; xnorVectors[1] _ [i0: L, i1: H, out: L]; xnorVectors[2] _ [i0: H, i1: L, out: L]; xnorVectors[3] _ [i0: H, i1: H, out: H]; GeneralPurposeTest["DpBuf", bufVectors]; GeneralPurposeTest["DpInv", invVectors]; GeneralPurposeTest["DpOr", orVectors]; GeneralPurposeTest["DpNor", norVectors]; GeneralPurposeTest["DpAnd", andVectors]; GeneralPurposeTest["DpNand", nandVectors]; GeneralPurposeTest["DpXor", xorVectors]; GeneralPurposeTest["DpXNor", xnorVectors]; <> <> <> <> <> <> <> <> <> <> <> <<>> <> <> <> <> <<>> <> <<>> <> <> <<>> <> <> <<>> <> <> <> <> <<>> <> <> <> <> <<>> <> <> <<>> <> <> }; TestLatch: PROC = { cell: Core.CellType; out0: ROPE _ CoreName.RopeNm["out0"]; ctl1: ROPE _ CoreName.RopeNm["1"]; XNode: ROPE _ CoreName.RopeNm["XNode"]; rec: CoreClasses.RecordCellType; latchVectors: TestVectors _ NEW[TestVectorSeq[8]]; latchVectors[0] _ [c1: H, c0: H, i0: L, out: L]; latchVectors[1] _ [c1: H, c0: L, i0: L, out: L]; latchVectors[2] _ [c1: H, c0: L, i0: H, out: L]; latchVectors[3] _ [c1: H, c0: H, i0: H, out: H]; latchVectors[4] _ [c1: H, c0: L, i0: H, out: H]; latchVectors[5] _ [c1: H, c0: L, i0: L, out: H]; latchVectors[6] _ [c1: H, c0: H, i0: L, out: L]; latchVectors[7] _ [c1: H, c0: L, i0: L, out: L]; cell _ Extract["DpLatch"]; rec _ NARROW[cell.data]; FOR ii: INT IN [0..rec.size) DO gate, ch1, ch2: ROPE; IF rec[ii].type.class#CoreClasses.transistorCellClass THEN Signal[]; gate _ CoreName.WireNm[rec[ii].actual[0]].n; ch1 _ CoreName.WireNm[rec[ii].actual[1]].n; ch2 _ CoreName.WireNm[rec[ii].actual[2]].n; IF (gate=ctl1 OR gate=out0) AND (ch1=XNode OR ch2=XNode) THEN [ ] _ Rosemary.SetTransistorInstanceSize[rec[ii], driveWeak]; ENDLOOP; Simulate[cell, latchVectors]}; library: CoreLibrary.Library _ CoreLibrary.OpenLibrary["IFUCore"]; <> TestLatch[]; TestSAdder[]; END.