CoreName:
CEDAR
DEFINITIONS
ROPE: TYPE = Core.ROPE;
Wire: TYPE = Core.Wire;
Wires: TYPE = Core.Wires;
CellType: TYPE = Core.CellType;
RopeNm: PROC[ rope: ROPE] RETURNS[registered: ROPE];
WireNm: PROC[wire: Wire, rope: ROPE←NIL] RETURNS[w: Wire, n: ROPE];
CellNm: PROC[cell: CellType, rope: ROPE←NIL] RETURNS[c: CellType, n: ROPE];
ID: PROC[ rope: ROPE] RETURNS[unique: ROPE];
Context: TYPE = SymTab.Ref; -- Name to Wire
NewContext: PROC RETURNS[ctx: Context];
CtxWire: PROC[ctx: Context, name: ROPE, size: INT ← -1] RETURNS[wire: Wire];
CtxRegisterWire: PROC[ctx: Context, wire: Wire, name: ROPE ← NIL]RETURNS[ok: BOOL];
CtxCopyWire: PROC[ctx: Context, wire: Wire] RETURNS[new: Wire];
CtxWireToName: PROC[ctx: Context, wire: Wire] RETURNS[name: ROPE];
CtxNameToWire: PROC[ctx: Context, name: ROPE] RETURNS[wire: Wire];
WiresFromCtx: PROC[ctx: Context] RETURNS[wires: Wires];
WireFromCtx: PROC[ctx: Context] RETURNS[wire: Wire];
KillContext: PROC[ctx: Context] RETURNS[Context];
BindModules:
PROC[public: Wire, modules:
LIST
OF CellType, name:
ROPE ←
NIL]
RETURNS [cell: CellType]; -- using atomic names
RelativeSignal:
TYPE =
RECORD[
pol: Polarity ← unk,
ph: Ph ← unk ];
cycle: INT ← unk ];
unk: INT = -1;
Ph: TYPE = {A, AB, ABB, ABBB, Ac, B, BA, BAA, BAAA, Bc, unk};
Polarity: TYPE = {pos, neg, unk};
PhRope: ARRAY Ph OF ROPE;
PolarityRope: ARRAY Polarity OF ROPE;
BitRope foo.bar.cnt foo.bar.2
SigRope FooBarCnt FooBar.2
Signal NotFooBarCntAB NotFooBarAB.2
Signal: TYPE = REF SigRec;
SigRec: TYPE = RECORD[not: BOOL←FALSE, root: ROPE←NIL, ph: Ph←unk, cy, idx: INT←-1];
SelectName: PROC[inv: BOOL, posNm, negNm: ROPE] RETURNS [inverted: BOOL, name: ROPE];
SigName: PROC[sigRec: SigRec] RETURNS [name: ROPE ← NIL];
NameSig: PROC[name: ROPE] RETURNS [sigRec: SigRec ← [ ]];
NormalFormatNames:
PROC [format: REFBit.FormatRec]
RETURNS[name, nameInv: ROPE, dual, inverted: BOOL, cy, idx: INT];
SignalName: PROC[not: BOOL, pos, neg: ROPE, ph: Ph, cy: INT←-1] RETURNS [name: ROPE];
ParseSignalName: PROC[name: ROPE] RETURNS [not: BOOL, root: ROPE, ph: Ph, cy: INT];
BitRopeToSigRope: PROC[name: ROPE] RETURNS [ROPE];
RootExt: PROC[name: ROPE] RETURNS [root, ext: ROPE];
EDTypeWire: PROC[root, ext, ref: ROPE] RETURNS[wire: Wire];
END.