PLASimImpl.mesa,
Copyright c 1986 by Xerox Corporation. All rights reserved.
Last Edited by Curry, October 22, 1986 3:47:06 pm PDT
Don Curry October 31, 1986 1:23:48 pm PST
Last Edited by: Louis Monier February 10, 1987 7:34:53 pm PST
PLASimImpl:
CEDAR
PROGRAM
IMPORTS CoreCreate, CoreFlat, CoreIO, CoreOps, IO, PLAOps, Ports, REFBit, Rope, Rosemary, TerminalIO
EXPORTS PLASim =
BEGIN
ROPE: TYPE = Core.ROPE;
simplePLARoseClass: ROPE ← Rosemary.Register ["SimplePLA", SimplePLAInit, SimplePLAEval];
simplePLAClass:
PUBLIC Core.CellClass ←
Rosemary.BindCellClass[
CoreIO.RegisterClass[
CoreOps.SetClassPrintProc[
class: NEW[ Core.CellClassRec ← [name: "SimplePLA", layersProps: FALSE]],
proc: PrintSimplePLACell],
WriteSimplePLACell,
ReadSimplePLACell ],
simplePLARoseClass];
WriteSimplePLACell: CoreIO.ClassWriteProc =
{CoreIO.WriteRope[h, NARROW[cellType.data]]};
ReadSimplePLACell: CoreIO.ClassReadProc =
{cellType.data ← CoreIO.ReadRope[h]};
PrintSimplePLACell: CoreOps.PrintClassProc =
{name: ROPE ← NARROW [data]; out.PutF["PLA File: %g.ttt", IO.rope[name]]};
inputs: NAT = 0;
ninputs: NAT = 1;
outputs: NAT = 2;
CreateSimplePLAPublic:
PUBLIC
PROC[name:
ROPE, additionalPublics: Core.Wires ←
NIL]
RETURNS[public: Core.Wire] = {
pla: PLAOps.PLA ← PLAOps.ReadPLAFile[name.Cat[".ttt"]];
nofIns: INT ← REFBit.Size[pla.data];
nofOuts: INT ← REFBit.Size[pla.out];
publics: Core.Wires ←
LIST [
CoreCreate.Seq["in", nofIns],
CoreCreate.Seq["nin", nofIns],
CoreCreate.Seq["out", nofOuts],
CoreCreate.Seq["GND", 0],
CoreCreate.Seq["VDD", 0] ];
publics.rest.rest.rest.rest.rest ← additionalPublics;
public ← CoreOps.CreateWire[publics]};
CreateSimplePLA:
PUBLIC
PROC[name:
ROPE, public: Core.Wire]
RETURNS[cellType: Core.CellType] = {
cellType ←
NEW [ Core.CellTypeRec ← [
class: simplePLAClass,
public: public,
data: name ] ]};
badInsList: LIST OF PLASim.SimplePLAState ← NIL;
SetUpRose:
PUBLIC PROC[cell: Core.CellType] = {
dummy: Core.Wire ← CoreOps.FindWire[cell.public, "DisChg"];
IF cell.class#simplePLAClass THEN Signal[];
IF dummy#
NIL
THEN
[]←Ports.InitPort[wire: dummy, levelType: l, initDrive: none];
[]←Ports.InitPort[wire: cell.public[inputs], levelType: bs, initDrive: none];
[]←Ports.InitPort[wire: cell.public[ninputs], levelType: bs, initDrive: none];
[]←Ports.InitPort[wire: cell.public[outputs], levelType: bs, initDrive: drive];
[]𡤌oreFlat.CellTypeCutLabels[cell, simplePLARoseClass]};
BadIns:
PUBLIC PROC
RETURNS[
BOOL] = {
FOR list:
LIST
OF PLASim.SimplePLAState ← badInsList, list.rest
WHILE list #
NIL
DO
IF list.first.badIns THEN RETURN[TRUE];
ENDLOOP;
RETURN[FALSE]};
BadInsReset: PUBLIC PROC = {badInsList ← NIL};
SimplePLAInit: Rosemary.InitProc = {
s: PLASim.SimplePLAState;
pla: PLAOps.PLA;
name: ROPE ← NARROW[cellType.data];
IF oldStateAny # NIL THEN RETURN[oldStateAny]; -- no real state in SimplePLAStateRec
pla ← PLAOps.ReadPLAFile[name.Cat[".ttt"] , TerminalIO.CreateStream[]];
s ←
NEW[PLASim.SimplePLAStateRec ← [
pla: pla,
in: CoreOps.GetWireIndex[cellType.public, "in"],
nin: CoreOps.GetWireIndex[cellType.public, "nin"],
out: CoreOps.GetWireIndex[cellType.public, "out"] ] ];
s.inSize ← cellType.public[s.in].size;
s.outSize ← cellType.public[s.out].size;
badInsList ← CONS[s, badInsList];
RETURN[s]};
SimplePLAEval: Rosemary.EvalProc = {
s: PLASim.SimplePLAState ← NARROW[stateAny];
FOR i: INT IN [0..s.inSize) DO
REFBit.Set[s.pla.data, i, p[s.in].bs[i]] ENDLOOP;
PLAOps.GetOutForData[s.pla];
FOR i: INT IN [0..s.outSize) DO
p[s.out].bs[i] ← NOT REFBit.Get[s.pla.out, i] ENDLOOP };
NOR NOR arrays => Inverted outputs
SimplePLAEval: Rosemary.EvalProc = {
s: PLASim.SimplePLAState ← NARROW[stateAny];
s.badIns ← FALSE;
FOR i:
INT
IN [0..s.inSize)
DO
IF p[s.in].bs[i] = p[s.nin].bs[i] THEN s.badIns ← TRUE;
REFBit.Set[s.pla.data, i, p[s.in].bs[i]] ENDLOOP;
PLAOps.GetOutForData[s.pla];
FOR i:
INT
IN [0..s.outSize)
DO p[s.out].bs[i] ←
NOT REFBit.Get[s.pla.out, i]
ENDLOOP };
NOR NOR arrays => Inverted outputs
Signal: SIGNAL = CODE;
END.