<> <> DIRECTORY Core, CoreCreate; IFUSim: CEDAR DEFINITIONS = BEGIN FormalIFU: PROC[public: Core.Wire _ NIL, quick, raw: BOOL] RETURNS[ifu: Core.CellType]; < .7).>> <> <> SetUp: PROC[cell: Core.CellType]; <<>> < 31, 40 => 32>> Adj: PROC[dec: INT] RETURNS[oct: INT _ 0]; SubstituteRecasted: PROC [cell: Core.CellType] RETURNS[recasted: Core.CellType]; MarkGatedTransistorsWeak: PROC [cell: Core.CellType, wr: CoreCreate.WR] RETURNS[count: INT _ 0]; FetchBufInitPort: PROC[cell: Core.CellType]; StackBufInitPort: PROC[cell: Core.CellType]; END.