BEGIN
FormalIFU: PROC[public: Core.Wire ← NIL, quick: BOOL] RETURNS[ifu: Core.CellType];
Marks weak transistors based on l/w ratio (> .7).
For Specific cellTypes: DrLatch
Marks special weak transistors, port types and drives, cutset and rose class
SetUp: PROC[cell: Core.CellType];
Adjustment for octal rope incorrectly converted using base 10. eg. 37 => 31, 40 => 32
Adj: PROC[dec: INT] RETURNS[oct: INT ← 0];
SubstituteRecasted: PROC [cell: Core.CellType] RETURNS[recasted: Core.CellType];
MarkGatedTransistorsWeak:
PROC [cell: Core.CellType, wr: CoreCreate.WR]
RETURNS[count: INT ← 0];
FetchBufInitPort: PROC[cell: Core.CellType];
StackBufInitPort: PROC[cell: Core.CellType];
END.