DIRECTORY Cabbage, Core, CoreCreate, CoreOps, DP, DragOpsCross, IFUSch, IO, PWCore, Route, TerminalIO; IFUSchImpl: CEDAR PROGRAM IMPORTS Cabbage, CoreCreate, CoreOps, DP, IO, PWCore, Route, TerminalIO EXPORTS IFUSch = BEGIN IFUVersion: NAT = 2; Wire: TYPE = Core.Wire; Wires: TYPE = Core.Wires; LayoutWithOutCabbageSignals: PUBLIC PWCore.LayoutProc = { TerminalIO.PutF["\nBEGIN: LayoutWithOutCabbageSignals: %g\n", IO.time[]]; obj _ PWCore.Layout[cellType ! Cabbage.Signal => {TerminalIO.PutF["*** Cabbage Signal: %g\n", IO.rope[explanation]]; RESUME}; Route.Signal => {TerminalIO.PutF["*** Route Signal: %g\n", IO.rope[explanation]]; RESUME} ]; TerminalIO.PutF["\nEND: LayoutWithOutCabbageSignals: %g\n", IO.time[]]}; zero: Wire _ CoreOps.CreateWires[ size: 0, name: "Gnd"]; one: Wire _ CoreOps.CreateWires[ size: 0, name: "Vdd"]; Variable: PROC[result, var: Wire, bias, scale: INT] = { first: NAT _ result.size - var.size; WHILE scale>1 DO first _ first-1; scale_scale/2 ENDLOOP; FOR i: NAT IN [0..var.size) DO result[first + i] _ var[i] ENDLOOP; FOR i: NAT DECREASING IN [0..result.size) DO IF (bias MOD 2) = 1 THEN IF result[i]=NIL THEN result[i] _ one ELSE ERROR ELSE IF result[i]=NIL THEN result[i] _ zero; bias _ bias/2 ENDLOOP}; WireConst: PUBLIC PROC [val, size: CARDINAL, name: Core.ROPE _ NIL] RETURNS[wire: Core.Wire] = { IF name=NIL THEN name _ IO.PutFR["Size%gConst%g", IO.int[size], IO.int[val]]; wire _ CoreOps.CreateWires[size, name]; FOR i: NAT DECREASING IN [0..wire.size) DO wire[i] _ (IF (val MOD 2)=1 THEN one ELSE zero); val _ val/2; ENDLOOP}; Version: PUBLIC DP.WIProc = {wire _ WireConst[IFUVersion, 8, "Version"]}; ABase: PUBLIC DP.WIProc = {wire _ WireConst[DragOpsCross.ProcessorRegister[euAux].ORD, 8, "ABase"]}; CBase: PUBLIC DP.WIProc = {wire _ WireConst[DragOpsCross.ProcessorRegister[euConstant].ORD, 8, "CBase"]}; NoStore: PUBLIC DP.WIProc = {wire _ WireConst[DragOpsCross.ProcessorRegister[euJunk].ORD, 8, "NoStore"]}; FlagBubble: PUBLIC DP.WIProc = { Byte: TYPE = [0..255]; ssw: DragOpsCross.StackedStatusWord _ [userMode: TRUE, trapsEnabled: FALSE]; bytes: PACKED ARRAY [0..4) OF Byte _ LOOPHOLE[ssw]; RETURN[WireConst[bytes[1], 8, "FlagBubble"]]}; MicroExcptJumps: PUBLIC DP.WIProc = { StateBA: Core.Wire _ CoreOps.CreateWires[ size: 8, name: "StateBA"]; StateNormBA: Core.Wire _ CoreOps.CreateWires[ size: 8, name: "StateNormBA"]; StateDelayBA: Core.Wire _ CoreOps.CreateWires[ size: 8, name: "StateDelayBA"]; MicroJump: Core.Wire _ WireConst[48, 8, "MicroJump"]; Resetting: Core.Wire _ WireConst[112, 8, "Resetting"]; Trap: Core.Wire _ WireConst[116, 8, "Trap"]; CJump: Core.Wire _ WireConst[120, 8, "CJump"]; FOR i: NAT IN [0..8) DO StateBA[i] _ StateNormBA[i] _ StateDelayBA[i] _ CoreOps.CreateWires[0] ENDLOOP; StateNormBA[0] _ zero; StateDelayBA[0] _ one; RETURN[CoreOps.CreateWire[ LIST[StateBA, StateNormBA, StateDelayBA, MicroJump, Resetting, Trap, CJump]]]}; Pipe0: PUBLIC DP.WIProc = { wires: Core.Wires _ LIST[ CoreOps.CreateWires[0, "EStkOverflow"], CoreOps.CreateWires[0, "InstFault"], CoreOps.CreateWires[0, "KIsRtOp"], CoreOps.CreateWires[0, "FCtlIsRtOp"], CoreOps.CreateWires[0, "Push"], CoreOps.CreateWires[0, "Pop"], CoreOps.CreateWires[0, "NX2ALitSrcNn"], CoreOps.CreateWires[0, "xxx"] ]; wire _ CoreOps.CreateWire[ wires, "Pipe0"]}; Pipe1: PUBLIC DP.WIProc = { EUAluOp: Wire _ CoreCreate.Seq[size: 4, name: "EUAluOp"]; wires: Core.Wires _ LIST[ (EUAluOp[0] _ CoreOps.CreateWires[0]), (EUAluOp[1] _ CoreOps.CreateWires[0]), (EUAluOp[2] _ CoreOps.CreateWires[0]), (EUAluOp[3] _ CoreOps.CreateWires[0]), CoreOps.CreateWires[0, "EUWriteToPBus"], CoreOps.CreateWires[0, "EUSt3AIsCBus"], CoreOps.CreateWires[0, "InstStarting"], CoreOps.CreateWires[0, "KPadsIn"] ]; wire _ CoreOps.CreateWire[ wires, "Pipe1"]; wire _ CoreOps.CreateWire[LIST[wire, EUAluOp]]}; Pipe2: PUBLIC DP.WIProc = { CondEffect: Wire _ CoreCreate.Seq[size: 2, name: "CondEffect"]; EUCondSel: Wire _ CoreCreate.Seq[size: 4, name: "EUCondSel"]; wires: Core.Wires _ LIST[ (EUCondSel[0] _ CoreOps.CreateWires[0]), (EUCondSel[1] _ CoreOps.CreateWires[0]), (EUCondSel[2] _ CoreOps.CreateWires[0]), (EUCondSel[3] _ CoreOps.CreateWires[0]), CoreOps.CreateWires[0, "DPCmndIsRd"], CoreOps.CreateWires[0, "CIsField"], (CondEffect[0] _ CoreOps.CreateWires[0]), (CondEffect[1] _ CoreOps.CreateWires[0]) ]; wire _ CoreOps.CreateWire[ wires, "Pipe2"]; wire _ CoreOps.CreateWire[LIST[wire, CondEffect, EUCondSel]]}; XopGen: PUBLIC DP.WIProc = { opAB: Wire _ CoreCreate.Seq[ size: 8, name: "OpAB"]; opGndAB: Wire _ CoreOps.CreateWires[ size: 32, name: "OpGndAB"]; xopPC: Wire _ CoreOps.CreateWires[ size: 32, name: "XopPC"]; wire _ CoreOps.CreateWire[LIST[opGndAB, xopPC]]; Variable[ result: opGndAB, var: opAB, bias: 0, scale: 1000000h]; Variable[ result: xopPC, var: opAB, bias: DragOpsCross.bytesPerWord * DragOpsCross.XopBase, scale: DragOpsCross.bytesPerWord * DragOpsCross.TrapWidthWords]}; TrapGen: PUBLIC DP.WIProc = { except: Wire _ CoreCreate.Seq[ size: 4, name: "ExceptCodeAB"]; cond: Wire _ CoreCreate.Seq[ size: 4, name: "EUCondSel3AB"]; fault: Wire _ CoreCreate.Seq[ size: 3, name: "DPFaultCodeAB"]; exceptPC: Wire _ CoreOps.CreateWires[ size: 32, name: "ExceptPCB"]; condPC: Wire _ CoreOps.CreateWires[ size: 32, name: "CondPCB"]; faultPC: Wire _ CoreOps.CreateWires[ size: 32, name: "FaultPCB"]; publics: Wires _ LIST[except, cond, fault, exceptPC, condPC, faultPC]; bias: INT _ DragOpsCross.bytesPerWord * DragOpsCross.TrapBase; scale: INT _ DragOpsCross.bytesPerWord * DragOpsCross.TrapWidthWords; Variable[result: exceptPC, var: except, bias: bias + scale*00B, scale: scale]; Variable[result: condPC, var: cond, bias: bias + scale*20B, scale: scale]; Variable[result: faultPC, var: fault, bias: bias + scale*40B, scale: scale]; wire _ CoreOps.CreateWire[publics]}; Dual: PUBLIC DP.WIProc = { wires: Core.Wires _ LIST[ CoreOps.CreateWires[0, "DualHi"], CoreOps.CreateWires[0, "DualLow"] ]; wire _ CoreOps.CreateWire[ wires, "Dual"]}; DP.RegisterWI["Version.icon", Version]; DP.RegisterWI["ABase.icon", ABase]; DP.RegisterWI["CBase.icon", CBase]; DP.RegisterWI["NoStore.icon", NoStore]; DP.RegisterWI["FlagBubble.icon", FlagBubble]; DP.RegisterWI["MicroExcptJumps.icon", MicroExcptJumps]; DP.RegisterWI["XopGen.icon", XopGen]; DP.RegisterWI["TrapGen.icon", TrapGen]; DP.RegisterWI["Dual.icon", Dual]; DP.RegisterWI["Pipe0.icon", Pipe0]; DP.RegisterWI["Pipe1.icon", Pipe1]; DP.RegisterWI["Pipe2.icon", Pipe2]; END. ΄IFUSchImpl.mesa Copyright c 1985 by Xerox Corporation. All rights reserved. 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