DIRECTORY CMosB, CoreCreate, IFUPublic, IFUSch, CommonPadFrame, CommonPGA176, IO, Route, TerminalIO; IFUPadFrame: CEDAR PROGRAM IMPORTS CoreCreate, IFUPublic, CommonPadFrame, CommonPGA176, IO, Route, TerminalIO EXPORTS IFUSch = BEGIN Wire: TYPE = CoreCreate.Wire; CellType: TYPE = CoreCreate.CellType; PGADescr: TYPE = CommonPGA176.PGADescr; pga176: PGADescr _ CommonPGA176.pga176; II: TYPE = IFUPublic.II; AddPads: PUBLIC PROC [inner: CellType] RETURNS [cellType: CellType] = { public: Wire _ IFUPublic.IfuInitializedPublic[TRUE]; xBus: Wire _ CoreCreate.Seq["XBus", 32]; ipAddr: Wire _ CoreCreate.Seq["iPAddr", 32]; ipData: Wire _ CoreCreate.Seq["iPData", 32]; dpFault: Wire _ CoreCreate.Seq["DPFaultB", 4]; dpCmd: Wire _ CoreCreate.Seq["DPCmnd2BAA", 8]; aluOp: Wire _ CoreCreate.Seq["EUAluOp2ABB", 4]; condSel: Wire _ CoreCreate.Seq["EUCondSel2ABB", 4]; dpFaultCode: Wire _ CoreCreate.Seq["DPFaultCodeBAA", 3]; onlyInternal: Wire _ CoreCreate.WireList[LIST[ -- for Cabbage "X2ASrcLit1BA", "KPadsIn3BA", dpFaultCode, -- Rt routing to feedback into inner xBus, "KPadsOut3BA", "KPadsIn4Ac", "NotKPadsIn4Ac", "NewFetchBAA", "IPRejectB", "IPFaultingB", ipData, ipAddr, dpCmd, "DPRejectB", dpFault, "UserMode2BAA", "Stage3ANormalBA", "NotDPRejectBA", aluOp, condSel, "EUCondition2B", "EURdFromPBus3ABB", "EUWriteToPBus3ABB", "ResetAB", "RescheduleAB", "phA", "phB", "prePhA", "prePhB", "preNotPhA", "preNotPhB", "clkPhA", "clkPhB", "dShA", "dShB", "dShRd", "dShWt", "dShIn", "dShOut" ]]; pga: PGADescr _ CommonPGA176.MakeCommonPGA176[]; -- this puts the power pads pga.SetPos[ pga176.left+14]; pga.SPad[ "IPReject", $In, ["toChip", "IPRejectB"]]; pga.SPad[ "IPFaulting", $In, ["toChip", "IPFaultingB"]]; pga.SPad[ "IPCmdFetch", $Out, ["fromChip", "NewFetchBAA"]]; pga.SPad[ "Reset", $In, ["toChip", "ResetAB"]]; pga.SPad[ "Reschedule", $In, ["toChip", "RescheduleAB"]]; pga.SetPos[ pga.globalPos+2]; pga.SPad[ "DShIn", $In, ["toChip", "dShIn"]]; pga.SPad[ "DShOut", $Out, ["fromChip", "dShOut"]]; pga.SPad[ "DShA", $In, ["toChip", "dShA"]]; pga.SPad[ "DShB", $In, ["toChip", "dShB"]]; pga.SPad[ "DShRd", $In, ["toChip", "dShRd"]]; pga.SPad[ "DShWt", $In, ["toChip", "dShWt"]]; pga.SetPos[ pga.globalPos+2]; pga.SPad[ "Vbb", $Analog]; pga.SPad[ "VbbGen", $VbbGen]; pga.SetPos[ pga176.bottom + 3]; FOR index: NAT IN [0..32) DO pga.SPad[ public[II[KBus].ORD][index], $IOTstIO, ["toChip", xBus[index]], ["fromChip", xBus[index]], ["phA", "phA"], ["enWA", "KPadsOut3BA"], ["phB", "phB"], ["enWB", "Vdd"], ["enRd", "KPadsIn4Ac"], ["disRd", "NotKPadsIn4Ac"], ] ENDLOOP; pga.SetPos[ pga176.right]; pga.SPad[ "Clk", $ClkGen, ["phA", "clkPhA"], ["phB", "clkPhB"], ["phADis", "clkPhB"], ["phBDis", "clkPhA"]]; pga.SPad[ "PhBOut", $Out, ["fromChip", "clkPhB"]]; pga.SPad[ "PhB", $DualIn, ["toChip", "prePhB"], ["toChipBar", "preNotPhB"]]; pga.SPad[ "PhAOut", $Out, ["fromChip", "clkPhA"]]; pga.SPad[ "PhA", $DualIn, ["toChip", "prePhA"], ["toChipBar", "preNotPhA"]]; pga.SPad[ "EUWriteToPBus", $Out, ["fromChip", "EUWriteToPBus3ABB"]]; pga.SPad[ "EURdFromPBus", $Out, ["fromChip", "EURdFromPBus3ABB"]]; pga.SPad[ "EUCondition", $In, ["toChip", "EUCondition2B"]]; FOR i: NAT IN [0..public[II[EUCondSel].ORD].size) DO pga.SPad[ public[II[EUCondSel].ORD][i], $Out, ["fromChip", condSel[i]]] ENDLOOP; FOR i: NAT IN [0..public[II[EUAluOp].ORD].size) DO pga.SPad[ public[II[EUAluOp].ORD][i], $Out, ["fromChip", aluOp[i]]] ENDLOOP; FOR i: NAT IN [0..public[II[DPCmd].ORD].size) DO pga.SPad[ public[II[DPCmd].ORD][i], $Gate3Out, ["fromChip", dpCmd[i]], ["enWA", "NotDPRejectBA"], ["enWB", "Stage3ANormalBA"]] ENDLOOP; pga.SPad[ "UserMode", $Out, ["fromChip", "UserMode2BAA"]]; pga.SPad[ "DPReject", $In, ["toChip", "DPRejectB"]]; FOR i: NAT IN [0..public[II[DPFault].ORD].size) DO pga.SPad[ public[II[DPFault].ORD][i], $In, ["toChip", dpFault[i]]] ENDLOOP; pga.SetPos[ pga176.top+3]; FOR index: NAT DECREASING IN [0..32) DO pga.SPad[ public[II[IPData].ORD][index], $IOTst, ["toChip", ipData[index]], ["fromChip", ipAddr[index]], ["phA", "phA"], ["enWA", "Vdd"], ["phB", "Gnd"], ["enWB", "Gnd"]] ENDLOOP; cellType _ CommonPadFrame.CreatePadFrame[ public: public, onlyInternal: onlyInternal, innerInstance: CoreCreate.InstanceList[inner, LIST[ ["PhA", "phA"], ["PhB", "phB"], ["PrePhA", "prePhA"], ["PrePhB", "prePhB"], ["PreNotPhA", "preNotPhA"], ["PreNotPhB", "preNotPhB"], ["IPAddr", "iPAddr"], ["IPData", "iPData"], ["DShA", "dShA"], ["DShB", "dShB"], ["DShRd", "dShRd"], ["DShWt", "dShWt"], ["DShIn", "dShIn"], ["DShOut", "dShOut"]]], pads: pga.pads, params: [ horizLayer: "metal", vertLayer: "metal2", nbPadsX: pga176.size, nbPadsY: pga176.size, library: "CommonPads.dale", centerDisplacement: [0*CMosB.lambda, 0*CMosB.lambda], outerBTChanWidth: 4 + 7*8, outerLRChanWidth: 4 + 6*8, powerBTCellWidth: 4 + 7*8 + 8+24+12+24+8, powerLRCellWidth: 4 + 6*8 + 8+100+12+100+8], name: "IFU" ! Route.Signal => {TerminalIO.PutF["*** Route SIGNAL: %g\n", IO.rope[explanation]]; RESUME} ] }; END. †IFUPadFrame.mesa Copyright Σ 1985, 1986, 1987 by Xerox Corporation. All rights reserved. Louis Monier March 11, 1987 12:59:02 pm PST Last Edited by: Louis Monier March 30, 1987 2:10:50 pm PST Last Edited by: Don Curry June 5, 1987 4:56:21 pm PDT -- Public wire -- Internal only wire -- Left side -- Bottom side: msb(0) on the left -- Right side: msb(0) on the bottom -- Top side Κ– "cedar" style˜šœ™JšœH™HJ™+J™:J™5—J˜JšΟk œ[˜dJ˜•StartOfExpansion[]šœ œ˜JšœK˜RJšœ ˜Jš˜J˜Jšœœ˜Jšœ œ˜&Jšœ œ˜'Jšœ(˜(Jšœœ œ˜J˜—šΟnœœœœ˜GJšΟb™Jšœ/œ˜5JšŸ™Jšœ.˜.Jšœ0˜0Jšœ0˜0Jšœ1˜1Jšœ0˜0Jšœ1˜1Jšœ4˜4J˜Jšœ8˜8šœ)œΟc˜@Jšœ+ $˜OJšœ3˜3Jšœ:˜:JšœP˜PJšœI˜IJšœ˜Jšœ ˜ Jšœ-˜-Jšœ˜Jšœ7˜7—J˜Jšœ1 ˜LJ™J™ Jšœ˜Jšœ9˜9Jšœ<˜˜>Jšœ5˜5Jšœ<˜