IFUDrivers.txt
Open IFUSrcComplete IFU2Impl IFUSrcFetchControler IFUSrcStackControler
Old Driver definitions
             Input  > clk Ouput  in ref out
Core To Control or Core To Pad (input) 
Positive          inv   >    inv  pos inv pos
Negative          inv-inv  >    inv  inv inv pos
Control To Core or Pad To Core (output) 
Positive  UnClocked     inv   > pos  inv  pos inv pos
Negative  UnClocked     inv   > inv  inv  inv pos pos
Positive  Clocked      inv-inv  > invClk inv  pos pos pos
Negative  Clocked      inv   > invClk inv wrng? pos inv pos
                     sb?  inv pos pos
Input
Positive        inv A -   inv* (invSing invDual)(pos inv pos)
Negative        inv2 B -   inv* (invSing invDual)(inv inv pos)
Output
Positive UnClocked    inv A pos  inv* (invSing invDual)(pos inv pos)
Negative UnClocked    inv2 B pos  inv* (invSing invDual)(inv inv pos)
Positive Clocked     inv2 B invAc inv* (invSing invDual)(pos pos pos)
Negative Clocked     inv B invBc  inv* (invSing invDual)(inv pos pos)
Driver components
    in  inv A pos  invSing
    out inv2 B inv  invDual
         invAc 
         invBc 
Driver types
PLAIn  ::= in  * inv pos  invDual
PLAInvOut ::= out * inv inv**  invSing
PLAPosOut ::= out * pos inv**  invSing
PassIn   ::= out * inv pos  invSing
PassOut  ::= in  * inv pos  invSing
Interlock
Record IFUPLAInterlock.InterlockIn
PLAIn  B
KIsRtOp1BA
FCtlIsRtOp1BA
CIsField2AB
CIsField3AB
DPCmndIsRd2BA
A1IsC2B
A1IsC3B
B1IsC2B
B1IsC3B
Record IFUPLAInterlock.InterlockOut
PLAInvOut B
Stage1BHoldBA
EUAluLeftSrc1BA
EUAluRightSrc1BA
EUStore2ASrc1BA
EUSt3AIsCBus1BA
MainPipeControl
RECORD IFUPLAMainPipeControl.MainPipeControlIn
PLAIn B
ResetBA
DPRejectBA
DPFaultingBA   ← DPFaultBA.0
ProtMicroCycleBA
MicroExcptJmpBubbleAB
Stage2BAbortAB
Stage1BHoldBA
CondEffect1BA.0 CondEffect1BA.1
CondEffect2BA.0 CondEffect2BA.1
EUCondition2BA
TrapsEnabled2BA  ← Flag2BA.7
EStkOverflow2BA
InstStarting2BA
RescheduleBA
RschWaitingAB
Push2AB
InstFault2BA
IStkNearlyFullBA
PLAIn A
RschClearAB
RECORD IFUPLAMainPipeControl.MainPipeControlOut
PLAInvOutDual B Stage2ABubbleBA    Stage2ANormalBA
PLAInvOutDual B Stage3AAbortBA     Stage3ANormalBA
PLAInvOut B  LoadStage1Ac
PLAInvOut B  LoadStage2Ac
PLAInvOut B  LoadStage3Ac
PLAPosOut A  NBcLoadStage1BA    ← LoadStageBc
PLAInvOutDual A Stage1BHoldingAB    NotStage1BHoldingAB
PLAInvOutDual A Stage2BAbortAB     Stage2BNormalAB
PLAInvOutDual A Stage3BCPipeAbortAB   Stage3BCPipeNormalAB
PLAInvOut A  MicroExcptJmpNoneAB
PLAInvOut A  MicroExcptJmpMicroJumpAB
PLAInvOut A  MicroExcptJmpBubbleAB
PLAInvOut A  MicroExcptJmpResettingAB
PLAInvOut A  MicroExcptJmpTrapAB
PLAInvOut A  MicroExcptJmpCJumpAB
PLAInvOut A  ExceptTypeSpecialCodeAB
PLAInvOut A  ExceptTypeCondCodeAB
PLAInvOut A  ExceptTypeDpFaultAB
PLAInvOut A  ExceptCodeAB.0
PLAInvOut A  ExceptCodeAB.1
PLAInvOut A  ExceptCodeAB.2
PLAInvOut A  ExceptCodeAB.3
PLAInvOut A  RschClearAB
PLAInvOut A  RschWaitingAB
StackControl
Record IFUPLAStackControl.StackBControlIn
PLAIn B    StackDiffBA
PLAIn B    MicroExcptJmpTrapAB
PLAIn B    Push3AB
PLAIn B    Pop3AB
Record IFUPLAStackControl.StackBControlOut
PLAInvOutDual B Push3BA
PLAInvOut B  Pop3BA
PLAInvOut B  IStkNearlyFullBA
Record IFUPLAStackControl.StackAControlIn
PLAIn B    X1ASrcStackBA
PLAIn B    X1ADstStackBA
PLAIn B    XBusStackEldestBA
PLAIn B    XBusStackLBA
PLAIn B    Push3BA
PLAIn B    Pop3BA
Record IFUPLAStackControl.StackAControlOut
PLAInvOutDual A StackAdjTosAB
PLAInvOut A  StackAddendIsOnesAB
PLAInvOut A  StackCarryIsOneAB
Record IFUPLAStackControl.StackDecodeIn
PLAIn B    BosBA
PLAIn B    TosBA
PLAIn B    X1ASrcStackBA
PLAIn B    X1ADstStackBA
PLAIn B    XBusStackEldestBA
PLAIn B    XBusStackLBA
PLAIn B    Push3BA
PLAIn B    Pop3BA
Record IFUPLAStackControl.StackDecodeRdOut
PLAInvOut B  StkRdAc
Record IFUPLAStackControl.StackDecodeWtLOut
PLAInvOut B  StkLdLAc
Record IFUPLAStackControl.StackDecodeWtPOut
PLAInvOut B  StkLdPAc
LtDrPadIO
DrToMid   IPRejectB     IPRejectBA
DrToMid   IPFaultingB    IPFaultingBA
DrFmMid   NewFetchBA    NewFetchBAA
DrToMidDual ResetAB     ResetBA
DrToMid   RescheduleAB   RescheduleBA
FetchControl
Record IFUPLAFetchControl.FetchControlIn
PLAIn   A
OpAB.0 OpAB.1 OpAB.2
FetchingBA silicon version
FetchBytesM1AB.0
FetchBytesM1AB.1
FetchBytesM1AB.2
FetchBytesM1AB.3
FetchBytesM1AB.4
PLAIn   B
NextMacroJumpBA
ResetBA
IPRejectBA
JumpPendingAB
FetchingAB simulation version
IPFaultedAB
IPFaultingBA
Record IFUPLAFetchControl.FetchControlOut
PLAInvOut  B
NewFetchBA
FetchingBA
FetchWtIndexCtlHoldBA FetchWtIndexCtlIncBA FetchWtIndexCtlClearBA
OpLengthbBA.0 OpLengthbBA.1 OpLengthbBA.2
InstFault0BA
PLAInvOut  A
JumpPendingAB
IPFaultedAB
JumpOffsetBetaAB JumpOffsetAlphaAB JumpOffsetAlphaBetaAB JumpOffsetXaAB
OpLengthAB.0 OpLengthAB.1 OpLengthAB.2
PLAPosOut  A
InstReadyAB
Record IFUPLAFetchControl.FetchWtDecodeIn
PLAIn   A
FetchingBA
FetchWtAB.0 FetchWtAB.1
Record IFUPLAFetchControl.FetchWtDecodeOut
PLAInvOut  A
FetchBufWtWdBc
Record IFUPLAFetchControl.FetchRdDecodeIn
PLAIn   B
FetchRdBA.0 FetchRdBA.1 FetchRdBA.2 FetchRdBA.3
Record IFUPLAFetchControl.FetchRdDecodeOut
PLAInvOut  B
FetchBufRdByteAc
RtDrPadIO
Record IFUPLARtDrPadIO.RtDrPadIO
DrToMid   DPRejectB   DPRejectBA
DrToMid   DPFaultB.3   DPFaultBA.3
DrToMid   DPFaultB.2   DPFaultBA.2
DrToMid   DPFaultB.1   DPFaultBA.1
DrToMid   DPFaultB.0   DPFaultBA.0
DrFmMid   DPFaultBA.3   DPFaultBAA.3
DrFmMid   DPFaultBA.2   DPFaultBAA.2
DrFmMid   DPFaultBA.1   DPFaultBAA.1
DrToMid   DPFaultBAA.3  DPFaultAB.3
DrToMid   DPFaultBAA.2  DPFaultAB.2
DrToMid   DPFaultBAA.1  DPFaultAB.1
DrFmMid   DPCmnd2BA.7  DPCmnd2BAA.7
DrFmMid   DPCmnd2BA.6  DPCmnd2BAA.6
DrFmMid   DPCmnd2BA.5  DPCmnd2BAA.5
DrFmMid   DPCmnd2BA.4  DPCmnd2BAA.4
DrFmMid   DPCmnd2BA.3  DPCmnd2BAA.3
DrFmMid   DPCmnd2BA.2  DPCmnd2BAA.2
DrFmMid   DPCmnd2BA.1  DPCmnd2BAA.1
DrFmMid   DPCmnd2BA.0  DPCmnd2BAA.0
DrFmMid   Flag2BA.6   UserMode2BAA
DrFmMid   EUAluOp2AB.3  EUAluOp2ABB.3
DrFmMid   EUAluOp2AB.2  EUAluOp2ABB.2
DrFmMid   EUAluOp2AB.1  EUAluOp2ABB.1
DrFmMid   EUAluOp2AB.0  EUAluOp2ABB.0
DrFmMid   EUCondSel2AB.3  EUCondSel2ABB.3
DrFmMid   EUCondSel2AB.2  EUCondSel2ABB.2
DrFmMid   EUCondSel2AB.1  EUCondSel2ABB.1
DrFmMid   EUCondSel2AB.0  EUCondSel2ABB.0
DrToMid   EUCondition2B  EUCondition2BA
DrFmMid   EUWriteToPBus3AB EUWriteToPBus3ABB
DrFmMid   EURdFromPBus3AB EURdFromPBus3ABB
DrFmMidInv  KPadsIn3BA   KPadsOut3BA
DrFmMidDual KPadsIn3BA   KPadsIn4Ac
DrFmMid   X2ASrcLit1BA  X2ASrcLit1BAA
DrToMidDual X2ASrcLit1BAA  X2ASrcLit2Ac
DrToMid   NIL     DebugABGD
DrToMid   NIL     DebugPC
DrToMid   NIL     DebugLSCF
DrToMid   NIL     DebugABStLim
InstrDecode
Record IFUPLAInstrDecode.InstrDecodeOut0
ExceptionalOutSignals[0] ← "
AluOpIsOp47BA  NotAluOpIsOp47BA
CondSelIsOp57BA  NotCondSelIsOp57BA
X1ASrcStackLAc NotX1ASrcStackLAc
X1ASrcStackPAc  NotX1ASrcStackPAc
X1ASrcSLimitAc  NotX1ASrcSLimitAc
X1ADstSLimitAc
X1ADstStackBA  NotX1ADstStackBA ";
PLAInvOut  B
AluOpBA
AluOpIsOp47BA
CondSelBA
CondSelIsOp57BA
CondEffect0BA
x1ADstSLimitBA
x1ASrcSLimitBA
X1ADstStackBA
X1ASrcStackBA
X1ASrcStackLBA -- not in simulation
X1ASrcStackPBA -- not in simulation
XBusStackLBA
XBusStackEldestBA
CIsField0BA
Record IFUPLAInstrDecode.InstrDecodeOut1
PLAInvOut  B
ARegLtBA
ARegRtBA
ARegOffBA
ARegModBA
Record IFUPLAInstrDecode.InstrDecodeOut2
PLAInvOut  B
BRegLtBA
BRegRtBA
BRegOffBA
BRegModBA
Record IFUPLAInstrDecode.InstrDecodeOut3
PLAInvOut  B
KIsRtOp0BA
FCtlIsRtOp0BA
PLAPosOut  B
NotPushScBA   
PLAInvOut  B
CRegLtBA
CRegRtBA
NotCRegOffBA.0
CRegOffBA.1
CRegOffBA.2
CRegModBA
Record IFUPLAInstrDecode.InstrDecodeOut4
PLAInvOut  B
FlagSrcBA
LSourceLtBA
LSourceRtBA
SSourceLtBA
SSourceRtBA
PopSaBA
PopSbBA
Record IFUPLAInstrDecode.InstrDecodeOut5
PLAInvOut  B
InstStarting0BA
MicroCycleNextBA
ProtMicroCycleBA
Pop0BA
DPCmndBA
DPCmndIsRd0BA
DPCmndSelBA
Record IFUPLAInstrDecode.InstrDecodeOut6
PLAInvOut  B
NextMacroBA
PCNextBA
PLAInvOutDual  B
PCBusSrcBA
PLAInvOut  B
PCPipeSrcBA
PLAInvOutDual  B
X2ALitSourceBA
PLAInvOut  B
KPadsIn0BA
Push0BA
ExceptionalOutSignals[6] ← "
PcBusSrcOffSetPCBA  NotPcBusSrcOffSetPCBA
PcBusSrcPipe3BA   NotPcBusSrcPipe3BA
PcBusSrcStackBA   NotPcBusSrcStackBA
PcBusSrcXopGenBA   NotPcBusSrcXopGenBA
PcBusSrcTrapGenBA  NotPcBusSrcTrapGenBA
PcBusSrcAlpBetGamDelBA NotPcBusSrcAlpBetGamDelBA
PcBusSrcXBA    NotPcBusSrcXBA
PcBusSrcPcBA    NotPcBusSrcPcBA
X2ALitSourceNone0BA  NotX2ALitSourceNone0BA ";
Record IFUPLAInstrDecode.InstrDecodeIn
PLAIn   A
StateAB
InstReadyAB
OpAB
AlphaAB
BetaAB
PushPendingAB
PopPendingAB
UserMode0AB ← FlagAB.6