GenInstrDecodePLA2:
PUBLIC GenInstrDecodePLAProc = {
instr: BoolExpr;
userMode0: BoolExpr ← BE[m:[userMode0: TRUE], d:[userMode0: TRUE]];
current ← old;
Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dIN]], userMode0], out: MultiByteXop];
Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dIN]], Not[userMode0]], out: [
aReg: abStackTop,
x2ALitSource: alpha,
cReg: cStackTop,
aluOp: VAdd,
dPCmnd: IOFetch,
dmCmndIsRd: TRUE ]];
Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dPIN]], userMode0], out: MultiByteXop];
Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dPIN]], Not[userMode0]], out: [
aReg: abStackTop,
x2ALitSource: alpha,
cReg: cStackTop,
aluOp: VAdd,
dPCmndSel: beta,
dPCmndIsRd0: TRUE ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dRB], out:[
aReg: abStackTop,
x2ALitSource: alpha,
cReg: cStackTop,
aluOp: VAdd,
dPCmnd: Fetch,
dPCmndIsRd0: TRUE ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dRSB], out:[
aReg: abStackTop,
x2ALitSource: alpha,
cReg: [ s, offset, one ],
pushSc: TRUE,
aluOp: VAdd,
dPCmnd: Fetch,
dPCmndIsRd0: TRUE
]];
Set[s:current, m:[op: InstrTopSig[4]], d:[op: dLRI0], out:[
aReg: [ l, op47 ],
x2ALitSource: alpha,
cReg: [ s, offset, one ],
pushSc: TRUE,
aluOp: VAdd,
dPCmnd: Fetch,
dPCmndIsRd0: TRUE ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dLGF], out:[
-- Save me for lisp
aReg: [ aBase , offset, zero ],
x2ALitSource: alphaBeta,
cReg: [ s, offset, one ],
pushSc: TRUE,
aluOp: VAdd,
dPCmnd: Fetch,
dPCmndIsRd0: TRUE ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dRRI], out:[
aReg: [ l, beta47],
x2ALitSource: alpha,
cReg: [ l, beta03 ],
aluOp: VAdd,
dPCmnd: Fetch,
dPCmndIsRd0: TRUE ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dRAI], out:[
aReg: [ aBase, beta47],
x2ALitSource: alpha,
cReg: [ l, beta03 ],
aluOp: VAdd,
dPCmnd: Fetch,
dPCmndIsRd0: TRUE ]];
instr ← And[current, BE[m:[op: InstrTopSig[8]], d:[op: dCST]]];
Set[s: instr, m:[state: ByteTopSig[8]], d:[state: 0], out:[
nextMacro: hold,
pcNext: fromPCBus,
microCycleNext: next,
x2ALitSource: zero,
aReg: [ cBase, offset, zero ],
bReg: [ s, offset, zero ],
aluOp: VAdd,
dPCmnd: IOStore ]];
Set[s: instr, m:[state: ByteTopSig[8]], d:[state: 1], out:[
nextMacro: hold,
pcNext: fromPCBus,
microCycleNext: next,
x2ALitSource: zero,
aReg: [ cBase, offset, one ],
bReg: [ s, offset, minus1 ],
aluOp: VAdd,
dPCmnd: IOStore ]];
Set[s: instr, m:[state: ByteTopSig[8]], d:[state: 2], out:[
x2ALitSource: alpha,
aReg: [ s, offset, minus2 ],
cReg: [ s, offset, one ],
pushSc: TRUE,
aluOp: VAdd,
dPCmnd: FetchSpecial,
dPCmndIsRd0: TRUE ]];
instr ← And[current, BE[m:[op: InstrTopSig[8]], d:[op: dCST]]];
Set[s: instr, m:[state: ByteTopSig[8]], d:[state: 0], out:[
nextMacro: hold,
pcNext: fromPCBus,
microCycleNext: next,
aReg: [ s, offset, minus2 ],
x2ALitSource: alpha,
cReg: [ s, offset, one ],
aluOp: VAdd,
dPCmnd: FetchHold,
dPCmndIsRd0: TRUE ]];
This cycle will invariably be Delayed (automatically) by the pipe since cycle 0 was a fetch into S+1
Set[s:instr, m:[state: ByteTopSig[8]], d:[state: 1], out:[
nextMacro: hold,
pcNext: fromPCBus,
microCycleNext: next,
aReg: [ s, offset, one ],
bReg: abStackTop,
aluOp: VSub,
condSel: EZ,
condEffect0: microJump ]]; -- IF [S+1] = [S] THEN microJump
Set[s:instr, m:[state: ByteTopSig[8]], d:[state: 2], out:NoOpMicro]; -- wait
Set[s:instr, m:[state: ByteTopSig[8]], d:[state: 3], out:NoOpMicro]; -- wait
Set[s:instr, m:[state: ByteTopSig[8]], d:[state: 4], out:[ -- [] ← ([S-2]+alpha)^, hold off, S←S+1
aReg: [ s, offset, minus2 ],
x2ALitSource: alpha,
pushSc: TRUE,
aluOp: VAdd,
dPCmnd: Fetch,
dPCmndIsRd0: TRUE ]];
Remember that when doing microjumps, you can't get next macro until the condition has been tested since the opcode must be the same (cycles 2 and 3 above are necessary).
([S-2]+alpha)^ ← [S-1], release hold, S ← S+1
This is the only conditional microcode jump in the whole machine at the moment, and the variable instr includes the conjunct that the microcycle number is < 48, which is not right, so the parameter s has to be built from scratch.
Set[s:And[BE[m: [instReady: TRUE], d: [instReady: TRUE]], BE[m: [op: InstrTopSig[8]], d: [op: dCST]]], m:[state: ByteTopSig[8]], d:[state: fixedMicroJump], out:[
aReg: [ s, offset, minus2 ],
bReg: [ s, offset, minus1 ],
x2ALitSource: alpha,
pushSc: TRUE,
aluOp: VAdd,
dPCmnd: Store ]];
Set[s: And[current,
BE[m:[op: InstrTopSig[8]], d:[op: dWB]]], out: [
aReg: abStackTop,
bReg: [ s, offset, minus1 ],
x2ALitSource: alpha,
popSa: TRUE,
popSb: TRUE,
aluOp: VAdd,
dPCmnd: Store ]];
Set[s: And[current,
BE[m:[op: InstrTopSig[8]], d:[op: dWSB]]], out: [
aReg: [ s, offset, minus1 ],
bReg: abStackTop,
x2ALitSource: alpha,
popSa: TRUE,
popSb: TRUE,
aluOp: VAdd,
dPCmnd: Store ]];
Set[s: And[current,
BE[m:[op: InstrTopSig[8]], d:[op: dPSB]]], out: [
aReg: [ s, offset, minus1 ],
bReg: abStackTop,
x2ALitSource: alpha,
popSa: TRUE,
aluOp: VAdd,
dPCmnd: Store ]];
Set[s: And[current,
BE[m:[op: InstrTopSig[4]], d:[op: dSRI0]]], out: [
aReg: [ l, op47 ],
bReg: abStackTop,
x2ALitSource: alpha,
popSb: TRUE,
aluOp: VAdd,
dPCmnd: Store ]];
Set[s: And[current,
BE[m:[op: InstrTopSig[8]], d:[op: dWRI]]], out: [
aReg: [ l, beta47],
bReg: [ l, beta03 ],
x2ALitSource: alpha,
aluOp: VAdd,
dPCmnd: Store ]];
Set[s: And[current,
BE[m:[op: InstrTopSig[8]], d:[op: dWAI]]], out: [
aReg: [ aBase, beta47],
bReg: [ l, beta03 ],
x2ALitSource: alpha,
aluOp: VAdd,
dPCmnd: Store ]];
General PBus operations
DA (2 stack oprnds) - Data and Address offset are stack operands
dIODA Write pcmnd: beta, addr: alpha + [S], data: [S-1] s←s-2
dIODA Read data: [S] ← pcmnd: beta, addr: alpha + [S]
D (1 stack oprnd) - Data is stack operand
dIOD Write pcmnd: beta, addr: alpha, data: [S] s←s-1
dIOD Read data: [S+1] ← pcmnd: beta, addr: alpha s←s+1
N (No stack oprnds) - No stack adjust - useful for signaling, repeated writes, etc.
dION Write pcmnd: beta, addr: alpha, data: [S]
dION Read data: [S+1] ← pcmnd: beta, addr: alpha
Set[s: And[current,
BE[m:[op: InstrTopSig[8]], d:[op: dIODA]],
BE[m:[beta:1],d:[beta:0]]], out: [
aReg: abStackTop,
popSa: TRUE,
cReg: cStackTop,
pushSc: TRUE, -- net effect is no push/pop
x2ALitSource: alpha,
aluOp: VAdd,
dPCmndSel: beta,
dPCmndIsRd0: TRUE]];
Set[s: And[current,
BE[m:[op: InstrTopSig[8]], d:[op: dIODA]],
BE[m:[beta:1], d:[beta:1]]],out:[
aReg: abStackTop,
popSa: TRUE,
bReg: [s, offset, minus1],
popSb: TRUE,
x2ALitSource: alpha,
aluOp: VAdd,
dPCmndSel: beta ]];
Set[s: And[current,
BE[m:[op: InstrTopSig[8]], d:[op: dIOD]],
BE[m:[beta:1], d:[beta:0]]], out: [
aReg: constantZero,
cReg: [s, offset, one],
pushSc: TRUE,
x2ALitSource: alpha,
aluOp: Or,
dPCmndSel: beta,
dPCmndIsRd0: TRUE]];
Set[s: And[current,
BE[m:[op: InstrTopSig[8]], d:[op: dIOD]],
BE[m:[beta:1], d:[beta:1]]], out: [
aReg: constantZero,
bReg: abStackTop,
popSb: TRUE,
x2ALitSource: alpha,
aluOp: Or,
dPCmndSel: beta ]];
Set[s: And[current,
BE[m:[op: InstrTopSig[8]], d:[op: dION]],
BE[m:[beta:1], d:[beta:0]]], out: [
aReg: constantZero,
cReg: [s, offset, one],
pushSc: TRUE, -- does this make any sense???
x2ALitSource: alpha,
aluOp: Or,
dPCmndSel: beta,
dPCmndIsRd0: TRUE]];
Set[s: And[current,
BE[m:[op: InstrTopSig[8]], d:[op: dION]],
BE[m:[beta:1], d:[beta:1]]], out: [
aReg: constantZero,
bReg: abStackTop,
x2ALitSource: alpha,
aluOp: Or,
dPCmndSel: beta ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dFSDB], out:[
aluOp: VAdd,
aReg: [s, offset, zero],
x2ALitSource: alphaBeta,
cReg: euField,
cIsField0: TRUE,
popSa: TRUE ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dLIB], out:[
x2ALitSource: alpha,
cReg: [ s, offset, one ],
pushSc: TRUE ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dLIDB], out:[
x2ALitSource: alphaBeta,
cReg: [ s, offset, one ],
pushSc: TRUE ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dLIQB], out:[
x2ALitSource: alpBetGamDel,
cReg: [ s, offset, one ],
pushSc: TRUE ]];
Set[s:current, m:[op: InstrTopSig[5]], d:[op: dLC0], out:[
bReg: [ cBase, op47 ],
cReg: [ s, offset, one ],
pushSc: TRUE ]];
Set[s:current, m:[op: InstrTopSig[6]], d:[op: dLC8], out:[
bReg: [ cBase, op47 ],
cReg: [ s, offset, one ],
pushSc: TRUE ]];
Set[s:current, m:[op: InstrTopSig[4]], d:[op: dLR0], out:[
bReg: [ l, op47 ],
cReg: [ s, offset, one ],
pushSc: TRUE ]];
Set[s:current, m:[op: InstrTopSig[4]], d:[op: dSR0], out:[
bReg: [ s, offset, zero ],
cReg: [ l, op47 ],
popSb: TRUE ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dDUP], out:[
bReg: abStackTop,
cReg: [ s, offset, one ],
pushSc: TRUE ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dEXDIS], out:[
bReg: abStackTop,
cReg: [ s, offset, minus1 ],
popSa: TRUE ]];
};