StackBufMain:
PROC [name:
ROPE]
RETURNS[cellType: Core.CellType] = {
Rename: CoreInstCell.RenameProc =
{RETURN[TranslateGenericSignal[old, sec, row, byte, bit]]};
sec, row, byte, bit: INT ← 0; -- must be here for Rename
library: CoreLibrary.Library ← IFUCoreCells.library;
genBit, genBitB, genBitV, genBitBV: Core.CellType;
genTop, genTopV, genMid, genMidV, genBot, genBotV, genBotBV: Core.CellType;
frame, section, secRow: CoreFrame.Frame;
generic: ARRAY [0..5) OF ARRAY [0..4) OF Core.CellType;
genBit ← CoreLibrary.Get[library, "DpStackBit", FALSE, LIST[ "none" ]];
genBitB ← CoreLibrary.Get[library, "DpStackBit", FALSE, LIST["Body", ]];
genBitBV ← CoreLibrary.Get[library, "DpStackBit", FALSE, LIST["Body", "ExtraVWire" ]];
genBitV ← CoreLibrary.Get[library, "DpStackBit", FALSE, LIST[ "ExtraVWire" ]];
genMid ← CoreLibrary.Get[library, "DpStackBitSeparation", FALSE, LIST[ "none" ]];
genMidV ← CoreLibrary.Get[library, "DpStackBitSeparation", FALSE, LIST[ "ExtraVWire" ]];
genTop ← CoreLibrary.Get[library, "DpStackBitTop", FALSE, LIST[ "none" ]];
genTopV ← CoreLibrary.Get[library, "DpStackBitTop", FALSE, LIST["Body", "ExtraVWire" ]];
genBot ← CoreLibrary.Get[library, "DpStackBitBot", FALSE, LIST[ "none" ]];
genBotV ← CoreLibrary.Get[library, "DpStackBitBot", FALSE, LIST[ "ExtraVWire" ]];
genBotBV ← CoreLibrary.Get[library, "DpStackBitBot", FALSE, LIST["Body", "ExtraVWire" ]];
generic[4] ← [genTopV, genTop, genTopV, genTopV];
generic[3] ← [genBitBV, genBitB, genBitBV, genBitBV];
generic[2] ← [genMidV, genMid, genMidV, genMidV];
generic[1] ← [genBitV, genBit, genBitV, genBitBV];
generic[0] ← [genBotV, genBot, genBotV, genBotBV];
cellType ← CoreFrame.NewFrameCell[5, name, [first: bottom]];
frame ← CoreFrame.FCT[cellType];
frame.seq[4] ← CoreFrame.NewFrameCell[1, "Top", [first: bottom]];
frame.seq[3] ← CoreFrame.NewFrameCell[16, "P", [first: bottom]];
frame.seq[2] ← CoreFrame.NewFrameCell[1, "Mid", [first: bottom]];
frame.seq[1] ← CoreFrame.NewFrameCell[16, "L", [first: bottom]];
frame.seq[0] ← CoreFrame.NewFrameCell[1, "Bot", [first: bottom]];
FOR sec
IN [0..5)
DO
section ← CoreFrame.FCT[frame.seq[sec]];
FOR row
IN [0..section.seq.size)
DO
section.seq[row] ← CoreFrame.NewFrameCell[32, NIL, [first: left]];
secRow ← CoreFrame.FCT[section.seq[row]];
FOR phyI:
INT
IN [0..32)
DO
temp: Core.CellType;
bit ← phyI / 4;
byte ← phyI MOD 4;
temp ← CoreInstCell.SpecificGeneric[generic[sec][byte], Rename];
secRow.seq[phyI] ← CoreFrame.NewFrameCell[0, NIL, [first: left, cell: temp] ];
ENDLOOP;
ENDLOOP;
ENDLOOP;
frame.cell ← CoreFrame.RecastFrameHard[cellType];
frame.seq ← NEW[CoreFrame.FrameSeq[0]];
[ ] ← CoreOps.VisitWire[frame.cell.public, BlockRightStkSignals]};
TranslateGenericSignal:
PROC[aName:
ROPE, sec, row, byte, bit:
INT]
RETURNS[ROPE]= {
sig: Sig ← NARROW[HashTable.Fetch[xlateTable, aName].value];
IF sig = NIL THEN Signal[];
SELECT sig^
FROM
vpass0 => RETURN[IO.PutFR["%g%01b", IO.rope[vPasses[0][byte]], IO.int[bit]]];
vpass1 => RETURN[IO.PutFR["%g%01b", IO.rope[vPasses[1][byte]], IO.int[bit]]];
hpass => RETURN[hPasses[sec][row]];
rd => RETURN[IO.PutFR["StkRdAc.%g", IO.int[row]]];
wt => RETURN[IO.PutFR["StkLd%gAc.%g", IO.rope[secRp[sec]], IO.int[row]]];
in =>
RETURN[
IO.PutFR["%
gStackWtDataA.%g%g",
IO.rope[secRp[sec]], IO.int[byte], IO.int[bit]]];
out =>
RETURN[
IO.PutFR["%
gStackRdDataA.%g%g",
IO.rope[secRp[sec]], IO.int[byte], IO.int[bit]]];
vdd => RETURN[aName];
gnd => RETURN[aName];
ENDCASE => ERROR};
secRp: ARRAY [0..5) OF ROPE = ["L", "L", "ERROR", "P", "P"];
vPasses:
ARRAY [0..2)
OF
ARRAY [0..4)
OF
ROPE =[
["XBus.0", "XBus.1", "XBus.2", "XBus.3"],
["OpBA.", NIL, "AlphaBA.", "BetaBA."] ];
hPasses:
ARRAY [0..5)
OF
ARRAY [0..16)
OF
ROPE =[
ALL[ NIL], [
"NextMacroGetBA", "NextMacroJumpBA", "NextMacroHoldBA", "ProtMicroCycleBA",
"X1ASrcStackBA", "X1ADstStackBA", "XBusStackEldestBA", "XBusStackLBA",
"RescheduleBA", "TrapsEnbled2BA", "RschWaiting2BA", "DPFaultBA.0",
Dummy[], "DPRejectBA", "EUCondition2BA", "InstReadyAB" ],
ALL[ NIL], [
"DebugOpStatus", "DShLeftOut", Dummy[], Dummy[],
Dummy[], Dummy[], Dummy[], Dummy[],
Dummy[], Dummy[], Dummy[], vbb,
pha, notpha, phb, notphb ],
ALL[ NIL] ];
Dummy: PROC RETURNS[ROPE] = {RETURN[CoreName.ID["Dummy"]]};
Sig: TYPE = REF SigType;
SigType: TYPE = {hpass, vpass0, vpass1, rd, wt, in, out, gnd, vdd};
xlateTable: HashTable.Table;
InitXlateTable:
PROC = {
Store:
PROC[refName:
ROPE, sigType: SigType] = {
refName ← CoreName.RopeNm[refName];
[] ← HashTable.Store[xlateTable, refName, NEW[SigType ← sigType]]};
xlateTable ← HashTable.Create[equal: HashTable.RopeEqual, hash: HashTable.HashRope];
Store[ "hPass", hpass];
Store[ "rd", rd];
Store[ "wt", wt];
Store[ "bus0", vpass0];
Store[ "bus1", vpass1];
Store[ "in0", in];
Store[ "out0", out];
Store[ "GND", gnd];
Store[ "VDD", vdd] };
InitXlateTable[];