IFUSrcABForm:
CEDAR
PROGRAM
IMPORTS CoreFrame, CoreName, IFUCoreData, IFUSrc
EXPORTS IFUSrc =
BEGIN
ROPE: TYPE = Core.ROPE;
GND: ROPE = CoreName.RopeNm["GND"];
VDD: ROPE = CoreName.RopeNm["VDD"];
xBus: ROPE = CoreName.RopeNm["XBus."];
alpha: ROPE = "AlphaBA.";
beta: ROPE = "BetaBA.";
zero: ROPE = GND;
one: ROPE = "(GND GND GND GND GND GND GND VDD)";
jmp48: LIST OF REF = IFUSrc.CardToList[ 48, 8];
jmp112: LIST OF REF = IFUSrc.CardToList[112, 8];
jmp116: LIST OF REF = IFUSrc.CardToList[116, 8];
jmp120: LIST OF REF = IFUSrc.CardToList[120, 8];
stateBAnorm:
ROPE =
"(GND StateBA.1 StateBA.2 StateBA.3 StateBA.4 StateBA.5 StateBA.6 StateBA.7 )";
stateBAdelay:
ROPE =
"(VDD StateBA.1 StateBA.2 StateBA.3 StateBA.4 StateBA.5 StateBA.6 StateBA.7 )";
aOffset: ROPE = "(ARegOffBA.0 ARegOffBA.0 ARegOffBA.0 ARegOffBA.0 ARegOffBA.0 ARegOffBA.0 ARegOffBA.1 ARegOffBA.2 )";
bOffset: ROPE = "(BRegOffBA.0 BRegOffBA.0 BRegOffBA.0 BRegOffBA.0 BRegOffBA.0 BRegOffBA.0 BRegOffBA.1 BRegOffBA.2 )";
aSum17: ROPE = "(GND ASum.1 ASum.2 ASum.3 ASum.4 ASum.5 ASum.6 ASum.7 )";
bSum17: ROPE = "(GND BSum.1 BSum.2 BSum.3 BSum.4 BSum.5 BSum.6 BSum.7 )";
alpha03: ROPE = "(GND GND GND GND AlphaBA.0 AlphaBA.1 AlphaBA.2 AlphaBA.3 )";
alpha47: ROPE = "(GND GND GND GND AlphaBA.4 AlphaBA.5 AlphaBA.6 AlphaBA.7 )";
beta03: ROPE = "(GND GND GND GND BetaBA.0 BetaBA.1 BetaBA.2 BetaBA.3 )";
beta47: ROPE = "(GND GND GND GND BetaBA.4 BetaBA.5 BetaBA.6 BetaBA.7 )";
op47: ROPE = "(GND GND GND GND OpBA.4 OpBA.5 OpBA.6 OpBA.7 )";
cBase: REF = IFUSrc.ProcRegToList[euConstant];
aBase: REF = IFUSrc.ProcRegToList[euAux];
gap13: ROPE = "( NIL Gap.1 Gap.2 Gap.3 NIL NIL NIL NIL )";
gap13BA: ROPE = "( NIL GapBA.1 GapBA.2 GapBA.3 NIL NIL NIL NIL )";
See also IFUSrcControlPipe.forthByteBA
forthByteBA:
ROPE = "(
EUSt3AIsCBus2BA
EUAluLeftSrc1BA.0 EUAluLeftSrc1BA.1
EUAluRightSrc1BA.0 EUAluRightSrc1BA.1 EUAluRightSrc1BA.2
EUStore2ASrc1BA.0 EUStore2ASrc1BA.1 )";
RtSwitchingTop:
LIST
OF
REF =
LIST[
xBus,
LIST[ op47, NIL, alpha, beta ],
"( LAB. SAB. C3AB. NIL )",
"( NIL NIL C2AB. NIL )",
"( NIL NIL C3BA. NIL )" ];
RtSwitching:
PROC
RETURNS[cellType: Core.CellType] = {
cellType ← IFUCoreData.CellProc[
subClass: "SwitchBox",
name: "RtSwitching",
top: RtSwitchingTop,
right: "(
StateAB.0 StateAB.1 StateAB.2 StateAB.3 StateAB.4 StateAB.5 StateAB.6 StateAB.7
ARegOffBA.0 ARegOffBA.1 ARegOffBA.2
BRegOffBA.0 BRegOffBA.1 BRegOffBA.2 )",
bot: RtArgFormMuxTop,
xform: IFUCoreData.Interleaved48 ]};
RtArgFormMuxTop:
LIST
OF
REF =
LIST[
xBus,
LIST[ op47, "C3AB.", alpha, beta ],
"( LAB. SAB. StateAB. NIL )",
LIST[ NIL, op47, NIL, "C2AB." ],
LIST[ aOffset, bOffset, "C3BA.", NIL ],
"( NIL NIL NIL NIL )",
GND, VDD,
LIST[ alpha, alpha, NIL, NIL ],
LIST[ beta, beta, NIL, NIL ],
LIST[ beta03, beta03, NIL, NIL ] ];
RtArgFormMux:
PROC
RETURNS[cellType: Core.CellType] = {
cellType ← IFUCoreData.CellProc[
subClass: "Mux",
name: "RtArgFormMux",
top: RtArgFormMuxTop,
right: "(
ARegRtOp47BA ARegRtAlphaBA ARegRtAlpha47BA
ARegRtOffsetBA ARegRtBetaBA ARegRtBeta03BA ARegRtBeta47BA
BRegRtOp47BA BRegRtAlphaBA BRegRtAlpha47BA
BRegRtOffsetBA BRegRtBetaBA BRegRtBeta03BA BRegRtBeta47BA )",
in:
LIST[
LIST[op47, NIL, NIL, NIL],
LIST[alpha, NIL, NIL, NIL],
LIST[alpha03, NIL, NIL, NIL],
LIST[alpha47, NIL, NIL, NIL],
LIST[aOffset, NIL, NIL, NIL],
LIST[beta, NIL, NIL, NIL],
LIST[beta03, NIL, NIL, NIL],
LIST[beta47, NIL, NIL, NIL],
LIST[NIL, op47, NIL, NIL],
LIST[NIL, alpha, NIL, NIL],
LIST[NIL, alpha03, NIL, NIL],
LIST[NIL, alpha47, NIL, NIL],
LIST[NIL, bOffset, NIL, NIL],
LIST[NIL, beta, NIL, NIL],
LIST[NIL, beta03, NIL, NIL],
LIST[NIL, beta47, NIL, NIL] ],
out: "( ( ASumRt. BSumRt. NIL NIL ) )",
bot: AdderTop,
xform: IFUCoreData.Interleaved48 ]};
AdderTop:
LIST
OF
REF =
LIST[
xBus,
LIST[ op47, "C3AB.", NIL, beta ],
"( LAB. SAB. StateAB. NIL )",
"( NIL NIL NIL C2AB. )",
"( NIL NIL C3BA. NIL )",
"( ASumRt. BSumRt. NIL NIL )" ];
Adder:
PROC
RETURNS[cellType: Core.CellType] = {
cellType ← IFUCoreData.CellProc[
subClass: "Adder",
name: "Adder",
top: AdderTop,
right: "( GND GND GND VDD )",
in:
LIST[
LIST[ "ASumRt.", "BSumRt.", one, "NotSLimitAB." ],
"( ASumLt. BSumLt. StateAB. SAB. )" ],
out: LIST[ LIST[ "ASum.", "BSum.", "SeqStateAB.", gap13 ] ],
bot: CrossConnLSTop,
xform: IFUCoreData.Interleaved48 ]};
CrossConnLSTop:
LIST
OF
REF =
LIST[
xBus,
LIST[ op47, "C3AB.", NIL, beta ],
"( LAB. SAB. StateAB. NotSLimitAB. )",
"( NIL NIL SeqStateAB. C2AB. )",
LIST[ "ASum.", "BSum.", "C3BA.", gap13 ],
"( ASumLt. BSumLt. NIL SAB. )" ];
CrossConnLS:
PROC
RETURNS[cellType: Core.CellType] = {
cellType ← IFUCoreData.CellProc[
subClass: "SwitchBox",
name: "CrossConnLS",
top: CrossConnLSTop,
left: NIL,
right: "( X1ADstSLimitAc )",
bot: LtArgFormTop,
xform: IFUCoreData.Interleaved48 ]};
LtArgFormTop:
LIST
OF
REF =
LIST[
xBus,
LIST[ op47, "C3AB.", NIL, beta ],
"( LAB. SAB. StateAB. NotSLimitAB. )",
"( SAB. LAB. SeqStateAB. C2AB. )",
LIST[ "ASum.", "BSum.", "C3BA.", gap13 ],
"( ASumLt. BSumLt. NIL X1ADstSLimitAc )" ];
LtArgForm:
PROC
RETURNS[cellType: Core.CellType] = {
cellType ← IFUCoreData.CellProc[
subClass: "Mux",
name: "LtArgForm",
top: LtArgFormTop,
right: "(
ARegLtCBaseBA ARegLtABaseBA ARegLtSBA ARegLtLBA ARegLtZeroBA
BRegLtCBaseBA BRegLtABaseBA BRegLtSBA BRegLtLBA BRegLtZeroBA )",
in:
LIST[
LIST[cBase, NIL, NIL, NIL],
LIST[aBase, NIL, NIL, NIL],
"( SAB. NIL NIL NIL )",
"( LAB. NIL NIL NIL )",
"( GND NIL NIL NIL )",
LIST[NIL, cBase, NIL, NIL],
LIST[NIL, aBase, NIL, NIL],
"( NIL SAB. NIL NIL )",
"( NIL LAB. NIL NIL )",
"( NIL GND NIL NIL )" ],
out: "( ( ASumLt. BSumLt. NIL NIL ) )",
bot: Mux0BTop,
xform: IFUCoreData.Interleaved48 ]};
Mux0BTop:
LIST
OF
REF =
LIST[
xBus,
LIST[ op47, "C3AB.", NIL, beta ],
"( NIL NIL StateAB. NotSLimitAB. )",
"( NIL NIL SeqStateAB. C2AB. )",
LIST[ "ASum.", "BSum.", "C3BA.", gap13 ],
"( NIL NIL NIL X1ADstSLimitAc )" ];
Mux0B:
PROC
RETURNS[cellType: Core.CellType] = {
cellType ← IFUCoreData.CellProc[
subClass: "Mux",
name: "Mux0B",
top: Mux0BTop,
right: "(
ARegModFullBA ARegModHalfBA
BRegModFullBA BRegModHalfBA
MicroCycleNextClearBA MicroCycleNextHoldBA MicroCycleNextNextBA )",
in:
LIST[
"( ASum. NIL NIL NIL )",
LIST[ aSum17, NIL, NIL, NIL ],
"( NIL BSum. NIL NIL )",
LIST[ NIL, bSum17, NIL, NIL ],
"( NIL NIL GND NIL )",
"( NIL NIL StateAB. NIL )",
"( NIL NIL SeqStateAB. NIL )" ],
out: "( ( ASumx. BSumx. StateB. NIL ) )",
bot: Latch0BTop,
xform: IFUCoreData.Interleaved48 ] };
Latch0BTop:
LIST
OF
REF =
LIST[
xBus,
LIST[ op47, "C3AB.", NIL, beta ],
"( NIL NIL StateAB. NotSLimitAB. )",
"( NIL NIL NIL C2AB. )",
LIST[ NIL, NIL, "C3BA.", gap13 ],
"( ASumx. BSumx. StateB. X1ADstSLimitAc )" ];
Latch0B:
PROC
RETURNS[cellType: Core.CellType] = {
cellType ← IFUCoreData.CellProc[
subClass: "GPRow",
name: "Latch0B",
type: "DpLatch",
top: Latch0BTop,
left: "( PhB VBB )",
in: LIST[ LIST[ "ASumx.", "BSumx.", "StateB.", gap13 ] ],
out: LIST[ LIST[ "A0BA.", "B0BA.", "StateBA.", gap13BA ] ],
bot: Mux1ATop,
xform: IFUCoreData.Interleaved48 ]};
Mux1ATop:
LIST
OF
REF =
LIST[
xBus,
LIST[ op47, "C3AB.", NIL, beta ],
"( NIL NIL StateAB. NotSLimitAB. )",
"( NIL NIL StateBA. C2AB. )",
LIST[ "A0BA.", "B0BA.", "C3BA.", gap13BA ],
"( NIL NIL NIL X1ADstSLimitAc )" ];
Mux1A:
PROC
RETURNS[cellType: Core.CellType] = {
cellType ← IFUCoreData.CellProc[
subClass: "Mux",
name: "Mux1A",
top: Mux1ATop,
left: "(
MicroExcptJmpNoneAB MicroExcptJmpBubbleAB MicroExcptJmpMicroJumpAB
MicroExcptJmpResettingAB MicroExcptJmpTrapAB MicroExcptJmpCJumpAB
GND )",
in:
LIST[
LIST[ NIL, NIL, stateBAnorm, NIL ],
LIST[ NIL, NIL, stateBAdelay, NIL ],
LIST[ NIL, NIL, jmp48, NIL ],
LIST[ NIL, NIL, jmp112, NIL ],
LIST[ NIL, NIL, jmp116, NIL ],
LIST[ NIL, NIL, jmp120, NIL ],
LIST[ NIL, NIL, NIL, NIL ] ],
out: "( ( NIL NIL StateA. NIL ) )",
bot: Latch1ATop,
xform: IFUCoreData.Interleaved48 ] };
Latch1ATop:
LIST
OF
REF =
LIST[
xBus,
LIST[ op47, "C3AB.", NIL, beta ],
"( NIL NIL StateAB. NotSLimitAB. )",
"( NIL NIL NIL C2AB. )",
LIST[ "A0BA.", "B0BA.", "C3BA.", gap13BA ],
"( NIL NIL StateA. X1ADstSLimitAc )" ];
Latch1A:
PROC
RETURNS[cellType: Core.CellType] = {
cellType ← IFUCoreData.CellProc[
subClass: "GPRow",
name: "Latch1A",
type: "( DpLatch DpLatch DpLatchCtl DpLatchCtl )",
top: Latch1ATop,
left: "( LoadStage1Ac VBB )",
in:
LIST[
"( A0BA. B0BA. StateA. XBus.3 )",
"( NIL NIL PhA X1ADstSLimitAc )"], -- LatchControl
out:
LIST[
"( A1AB. B1AB. StateAB. SLimitAB. )"],
bot: DebugABStLimTop,
xform: IFUCoreData.Interleaved48 ]};
DebugABStLimTop:
LIST
OF
REF =
LIST[
xBus,
LIST[ op47, "C3AB.", NIL, beta ],
"( NIL NIL StateAB. NotSLimitAB. )",
"( NIL NIL PhA C2AB. )",
LIST[ "A1AB.", "B1AB.", "C3BA.", gap13BA ],
"( NIL NIL NIL SLimitAB. )" ];
DebugABStLim:
PROC
RETURNS[cellType: Core.CellType] = {
cellType ← IFUCoreData.CellProc[
subClass: "GPRow",
name: "DebugABStLim",
type: "DpDebugDr",
top: DebugABStLimTop,
right: "( DebugABStLim )",
in: "( ( A1AB. B1AB. StateAB. SLimitAB. ) )",
out: "( XBus. )",
bot: Mux1BTop,
xform: IFUCoreData.Interleaved48 ]};
Mux1BTop:
LIST
OF
REF =
LIST[
xBus,
LIST[ op47, "C3AB.", NIL, beta ],
"( NIL NIL NIL NotSLimitAB. )",
"( NIL NIL PhA C2AB. )",
LIST[ "A1AB.", "B1AB.", "C3BA.", gap13BA ],
"( NIL NIL NIL SLimitAB. )" ];
Mux1B:
PROC
RETURNS[cellType: Core.CellType] = {
cellType ← IFUCoreData.CellProc[
subClass: "Mux",
name: "Mux1B",
top: Mux1BTop,
left: "( Stage1BHoldingAB NotStage1BHoldingAB)",
in: "( ( A1BA. B1BA. NIL NIL ) ( A1AB. B1AB. NIL NIL ) )",
out: "( ( A1B. B1B. NIL NIL ) )",
bot: ShiftNotSLimitTop,
xform: IFUCoreData.Interleaved48 ] };
ShiftNotSLimitTop:
LIST
OF
REF =
LIST[
xBus,
LIST[ op47, "C3AB.", NIL, beta ],
"( A1BA. B1BA. NIL NotSLimitAB. )",
"( NIL NIL PhA C2AB. )",
LIST[ NIL, NIL, "C3BA.", gap13BA ],
"( A1B. B1B. NIL SLimitAB. )" ];
ShiftNotSLimit:
PROC
RETURNS[cellType: Core.CellType] = {
cellType ← IFUCoreData.CellProc[
subClass: "SwitchBox",
name: "ShiftNotSLimit",
top: ShiftNotSLimitTop,
left: "(PhA)",
right: NIL,
bot: Latch1BTop,
xform: IFUCoreData.Interleaved48 ]};
Latch1BTop:
LIST
OF
REF =
LIST[
xBus,
LIST[ op47, "C3AB.", NIL, beta ],
"( A1BA. B1BA. NotSLimitAB. NIL )",
"( NIL NIL NIL C2AB. )",
LIST[ NIL, NIL, "C3BA.", gap13BA ],
"( A1B. B1B. SLimitAB. SLimitAB. )" ];
Latch1B:
PROC
RETURNS[cellType: Core.CellType] = {
cellType ← IFUCoreData.CellProc[
subClass: "GPRow",
name: "Latch1B",
type: "( DpLatch DpLatch DpLatchInv (DpLatchInv
DpLatchOr DpLatchOr DpLatchOr DpLatchOr DpLatchOr DpLatchOr DpLatchOr ) )",
top: Latch1BTop,
left: "( PhB VBB )",
in: "(
( A1B. B1B. SLimitAB.
( NStkOver.1 GapBA.1 GapBA.2 NIL NIL NIL NIL NIL))
(
NIL
NIL
NIL
( NIL NStkOver.2 GapBA.3 NIL NIL NIL NIL NIL)) )",
out: "(
( A1BA. B1BA. NotSLimitAB.
(EStkOverflow1BA NStkOver.1 NStkOver.2 NIL NIL NIL NIL NIL)) )",
bot: DistributeCTop,
xform: IFUCoreData.Interleaved48 ]};
DistributeCTop:
LIST
OF
REF =
LIST[
xBus,
LIST[ op47, "C3AB.", NIL, beta ],
"(A1BA. B1BA. NIL (EStkOverflow1BA NStkOver.1 NStkOver.2 NIL NIL NIL NIL NIL))",
"(NIL NIL NIL C2AB. )",
"(NIL NIL C3BA. (NStkOver.1 NStkOver.2 GapBA.3 GapBA.3 NIL NIL NIL NIL))",
"(A1B. B1B. NIL SLimitAB. )" ];
DistributeC:
PROC
RETURNS[cellType: Core.CellType] = {
cellType ← IFUCoreData.CellProc[
subClass: "SwitchBox",
name: "DistributeC",
top: DistributeCTop,
left: "( EStkOverflow1BA )",
right: NIL,
bot: CompareABCTop,
xform: IFUCoreData.Interleaved48 ]};
CompareABCTop:
LIST
OF
REF =
LIST[
xBus,
LIST[ op47, "C3AB.", NIL, beta ],
"( A1BA. B1BA. A1B. B1B. )",
"( C3AB. NIL NIL C2AB. )",
"( NIL NIL C3BA. NIL )",
"( A1B. B1B. C2AB. SLimitAB. )" ];
CompareABC:
PROC
RETURNS[cellType: Core.CellType] = {
cellType ← IFUCoreData.CellProc[
subClass: "GPRow",
name: "CompareABC",
type: "DpXor",
top: CompareABCTop,
left: "( PhA PhB )", old
in:
LIST[
"( A1B. B1B. A1B. B1B. )",
"( C3AB. C3AB. C2AB. C2AB. )"],
out:
LIST[
"( A1NeC3Bx. B1NeC3Bx. A1NeC2Bx. B1NeC2Bx. )"],
bot: CompareABCDisChgTop,
xform: IFUCoreData.Interleaved48 ]};
CompareABCDisChgTop:
LIST
OF
REF =
LIST[
xBus,
LIST[ op47, NIL, NIL, beta ],
"( A1BA. B1BA. NIL NIL )",
"( A1NeC3Bx. B1NeC3Bx. A1NeC2Bx. B1NeC2Bx. )",
"( NIL NIL C3BA. NIL )",
"( NIL NIL NIL SLimitAB. )" ];
CompareABCDisChg:
PROC
RETURNS[cellType: Core.CellType] = {
cellType ← IFUCoreData.CellProc[
subClass: "GPRow",
name: "CompareABCDisChg",
type: "DpDisChg",
top: CompareABCDisChgTop,
left: "( PhB )",
in:
LIST[
"( A1NeC3Bx. B1NeC3Bx. A1NeC2Bx. B1NeC2Bx. )"],
out:
LIST[
"( A1IsC3B B1IsC3B A1IsC2B B1IsC2B )"],
bot: CompareABCPreChgTop,
xform: IFUCoreData.Interleaved48 ]};
CompareABCPreChgTop:
LIST
OF
REF =
LIST[
xBus,
LIST[ op47, NIL, NIL, beta ],
"( A1BA. B1BA. NIL NIL )",
"( A1IsC3B B1IsC3B A1IsC2B B1IsC2B )",
"( NIL NIL C3BA. NIL )",
"( NIL NIL NIL SLimitAB. )" ];
CompareABCPreChg:
PROC
RETURNS[cellType: Core.CellType] = {
cellType ← IFUCoreData.CellProc[
subClass: "GPRow",
name: "CompareABCPreChg",
type: "DpPreChg",
top: CompareABCPreChgTop,
left: "( NotPhA )",
out:
LIST[
"( A1IsC3B B1IsC3B A1IsC2B B1IsC2B )"],
bot: SwitchOutComparesTop,
xform: IFUCoreData.Interleaved48 ]};
SwitchOutComparesTop:
LIST
OF
REF =
LIST[
xBus,
LIST[ op47, NIL, NIL, beta ],
"( A1BA. B1BA. NIL NIL )",
"( A1IsC3B B1IsC3B A1IsC2B B1IsC2B )",
"( NIL NIL C3BA. NIL )",
"( NIL NIL NIL SLimitAB. )" ];
SwitchOutCompares:
PROC
RETURNS[cellType: Core.CellType] = {
cellType ← IFUCoreData.CellProc[
subClass: "SwitchBox",
name: "SwitchOutCompares",
top: SwitchOutComparesTop,
left: "( A1IsC3B B1IsC3B A1IsC2B B1IsC2B )",
right: NIL,
bot: DriveSLimitTop,
xform: IFUCoreData.Interleaved48 ]};
DriveSLimitTop:
LIST
OF
REF =
LIST[
xBus,
LIST[ op47, forthByteBA, NIL, beta ],
"( A1BA. B1BA. NIL NIL )",
"( NIL NIL NIL NIL )",
LIST[ NIL, NIL, "C3BA.", forthByteBA ],
"( NIL NIL NIL SLimitAB. )" ];
DriveSLimit:
PROC
RETURNS[cellType: Core.CellType] = {
cellType ← IFUCoreData.CellProc[
subClass: "GPRow",
name: "DriveSLimit",
type: "DpTriDr",
top: DriveSLimitTop,
right: "( X1ASrcSLimitAc NotX1ASrcSLimitAc )",
in: LIST[LIST[ zero, zero, zero, "SLimitAB." ]],
out: LIST[xBus],
bot: DriveABCDTop,
xform: IFUCoreData.Interleaved48 ]};
DriveABCDTop:
LIST
OF
REF =
LIST[
xBus,
LIST[ op47, forthByteBA, NIL, beta ],
"( A1BA. B1BA. NIL NIL )",
"( NIL NIL NIL NIL )",
LIST[ NIL, NIL, "C3BA.", forthByteBA ] ];
DriveABCD:
PROC
RETURNS[cellType: Core.CellType] = {
cellType ← IFUCoreData.CellProc[
subClass: "GPRow",
name: "DriveABCD",
type: "DpTriDr",
top: DriveABCDTop,
left: "( PhB NotPhB )",
in: LIST[LIST[ "A1BA.", "B1BA.", "C3BA.", forthByteBA ]],
out: LIST[xBus],
bot: ABFormBot,
xform: IFUCoreData.Interleaved48 ]};
ABFormBot:
LIST
OF
REF =
LIST[
xBus,
LIST[ op47, forthByteBA, NIL, beta ] ];
ABForm:
PUBLIC
PROC
RETURNS[cellType: Core.CellType] = {
name: ROPE ← CoreName.RopeNm["IFUABForm"];
IF (cellType ← CoreFrame.ReadFrameCache[name])=
NIL
THEN {
cellType ← CoreFrame.NewFrameCells[
name: name,
rec: [first: top],
cells:
LIST[
RtSwitching[],
RtArgFormMux[],
Adder[],
CrossConnLS[],
LtArgForm[],
Mux0B[],
Latch0B[],
Mux1A[],
Latch1A[],
DebugABStLim[],
Mux1B[],
ShiftNotSLimit[],
Latch1B[],
DistributeC[],
CompareABC[],
CompareABCDisChg[],
CompareABCPreChg[],
SwitchOutCompares[],
DriveSLimit[],
DriveABCD[] ] ];
CoreFrame.WriteFrameCache[cellType]}};
END.