[Indigo]<Dragon>IFUPack>IFUNotes.tioga!14

IFUNotes.tioga

Don Curry November 2, 1986 6:15:12 pm PST

X's in Adder outputs caused by disconnected carry ins. Overlayed conditional objects.

X's in IPFetch. Pad gate - open in layout.

CoreFlat - (wire type none - interchange lines)

Rosemary, charge problem caused X's.

RetchRd index - Mux input wrong

LoadStage1Bc - Driver inverted

Tristate Pads - control transistor needs to be next to pad - probably no serious problem.

Drivers inverted - Debug controls

Pad Extraction incorrect for overlapping cells (Gates)

Pads redone

IPData - Pad Proc arguments reversed (in/out) pad = (out/in) chip

UserMode - unnecessarily gating, there to be consistant with DPCmd, removed

PreCharge Eval Proc - driver ← none when control false

Missing NotDPReject - (Need static check for nodes w/ no channel)

Wrong name used to build Formal cell (Pad-IPAddr > Pad-IPData)

DpDisChg - Clock must be next to GND in Discharge cells (ABCompare problem)

Missing '.' in IFUSrcFetch.FetchMuxB FetchAddrAB.

CRegOffSet.0 => NotCRegOffSet.0

Removed Inverter after FetchBuf

Grounded Dummy in StackBuf

Added drive control (=none) to StackBuf and FetchBuf Eval Procs

Added fire/fireV/nPC to PLA Desc and Drive records

LSForm FlagB mux input was GND. (had period)

Fetch decoders were upside down

routing of IDFireV and IDNotPhA at bottom of right column

missing '.' in XaPipeB0.30..37 Mux

defualt Port init is b => unused signal (DisChg) = X causes problem

init Stack to 0

PCFormTop - Sign extend Alpha and Beta NOT 7 but 0!

PushBA unintentional bind inside StackBControl (driver/pla body nameing, in/out same name)

A and B sign extend offsets

Data and control switched DpLatchCtl

DpLatch-G-= and DpLatch-V-= Eval Procs Aliased

Remove S from IFU Stack (can easily add back in)

Large Mux for LSForm had SBA and LBA (which were unrouted) rather than SAB and LAB

IFU2Impl IPFaultingBA ← p[II[IPFaultingB].ORD].b (was p[II[..].ORD].c = page fault)

ABForm StateAB - use PHA not LoadStage1Ac

Pruned TrapTest into Quick Test

Ran first part ~ 350 cycles

Remade IFUCore drivers, symetric, no DRC problems (expect no well contact where its in next cell)

Removed ifupagefault Assert in LizardRosemary5CheckSynchImpl

Moved to NewCore - CoreFlat - Rosemary - new checkpoints

CoreFlatImpl - no nameHack

RosemaryUser - cp cn

Extract - public wires unpredictable - enum pins leaves out Pad Pin

CoreIO - no wire props on import public

Deltas - Init

Put poly hack in IFUPads to get around CoreGeometry Enum

IFU.df - Bertrand > BringIFU

IFUsEU2.df

Note: CoreFlatScanner won't accept top level name, must be public.xxx rather than xxx

Added dummy control lines to muxes in Fetch and ABForm to Correct DRC errors

Sinumlated Hot and Precharded PLAs

DRC'd Library

Added/Tested TilingClass implementation of PLAbodies

Batch DRC Hack

Fixed micocode, IFU2Impl, IFUSrcXaForm to enable Literal of zero (instead of beta) ref: CST[#0]

Fixed precharged pla header problems (only with mulitple segments)

Fixed HOrFooter size

Redesize beefed up GPC (not yet included)

DRC DataCol and LeftCol Fixed errors LSForm ABForm PCFormTop, FetchIndexing, DriveGate

Marked library with driveWeak transistors

Rebuilt data column, still need to drc Right and rebuild Left (and maybe right)

Fixed Via/Via problem in GND DriveIn for Debug Controls

Found more poly cut/cut instances in Right Column (already fixed)

49 via flatness advisories in RightColumn

some library cells including HPlaHOr had unmarked driveWeak transitors

(wrong or no association to the text)

Ark-Rolyal finished UpOneLevel Pass with CST[#0] (274 instructions)

IFUPLAFetchControlImpl - gave reset a higher priority to set IPFaulted

? What is wrong with the internal of Fetchcontroler - apparently FetchingAB and NotFetchingAB both occur as two separate nodes which do not get separte version names - the public FetchingBA is ok.

Fixed CoreBlockImpl.ResolveNames to merge publics and rename iOnly when conflicts are detected.

Created IFUCaches.df

Fixed CoreBlockImpl.ResolveNames (match deleted publics in actuals)

Remember to try flat rewrite of internal in CoreBlockImpl

Fixed Fetch Indexing error (GND.) caused when changing locations of controls in mux

November 9, 1986 4:46:00 pm PST

Rebuild Left with corrected CoreBlockImpl

smodeled IFU

Started Sim with pla evals off

Works!! Seems to run a little faster!

Brought over new Caches to Ark-Royal (didn't get them before for some reason)

Started Ark-Royal - build complete then sim with all evals turned off

November 9, 1986 7:38:42 pm PST

Reset problems

put back in SimpleMux and try again

Ark-Royal didn't build heart or complete? - try again with RB IFUPack; ← IFUSrc.Complte[]

November 11, 1986 6:42:25 am PST

Worked with all but DrLatch, DpLatch and Muxes - (need to init internal dr latch state)

will now try removing DrLatch

November 11, 1986 8:10:01 am PST

DrLatch seems to be critical, wil now try muxes

November 11, 1986 5:19:00 pm PST

Didn't work. Try taking out just DpLatch

November 15, 1986 1:51:30 pm PST

Ark-Royal down - higher level caches stale and inaccessable

run w/o DpLatch Eval => missing pE weak -> added to settup and reran -> wt stack prblm

StackBuf bit cell, no weaks - also needed to add inverters on read line - PC and LS

Now need to rebuild PCBot LSForm and StackBuf

Changed Cluster2Impl to Flush shift registers

See if GP Extract to driveWeak is feasible

November 15, 1986 7:25:01 pm PST

Got PCFormBot wrong - order of procedures

(GP Extract to driveWeak put in about here)

November 16, 1986 10:05:10 am PST

OK running only mux eval proc

6 hr to build all transistors

5 hr to route (heart and complete)

25 th cycle cleared StackRdDataA

37 th cycle cleared last X (EStkOverflow1BA)

manually halted at 142

Monday - would not settle

probably due to mux glitch that set off latch cycle

added driveWeak to Mux setup

Checked using Thyme that two latches can safely disagree through two mux transistors.

Full Simulation Worked!! ~150 cycles

added driveWeak satellites to mux generator

rebuilt complete overnite

Forked tryout of SimplifyDesign

didn't seem to help size much even though there was a great flurry of activity especially on flipped pla tiles. I should probably try harder to prevent occurances of `only child' cells in the first place

Tuesday - November 18, 1986 11:29:11 am PST - Rebuilt Simulation halted at about cycle 4

probably due to X's in CondEffect1BA which confused MainPipeControl MicroExcptJump StateA

Try again to make sure CondEffect1BA gets cleared during reset by making sure LoadState1Bc

is enabled during reset.

Changed IFUPLAMainPipeControlImpl - generated new .ttt - rebuild left column

Why did this problem not show up yesterday.

Layout Mux changes should have been indistinguishable from IFUSim Setup.

Guess: Evaluation order sensitive? I don't believe it. Could be the sensitivity of the Instrdecode PLA to the evaluation sequence.

November 18, 1986 1:33:07 pm PST

It seems to be happy now - (cycle 26)

Will halt and do DRC

Tonite will build complete and Sim using Quick ← FALSE

November 19, 1986 10:48:09 am PST

Small glitch with quick vs routed pathes in IFUTestUtils - fixed

Seems to be happy now - Simulation of Routed at transistor level

November 20, 1986 6:39:06 pm PST

Error at cycle 250 => no global routing for NotResetBA and Stage1BNormat ?

Decremented power bus - turned out to be wrong channel

Decremented power bus - truned out to be in adequate

Decremented power bus - OK

Starting Simulation