<> <> <> DIRECTORY Core, Dragon, ICTest, IFUPublic, Ports, Rope; IFUChipTestReset: CEDAR PROGRAM IMPORTS ICTest = BEGIN II: TYPE = IFUPublic.II; QPh: TYPE = {A, ab, B, ba}; T: BOOL = TRUE; F: BOOL = FALSE; ifuChipTest: Rope.ROPE = "IFU Chip Test"; Cycle: PROC[p: Ports.Port, Eval: PROC [memory: BOOL _ TRUE]] = { ClockPh[A, p, Eval]; ClockPh[ab, p, Eval]; ClockPh[B, p, Eval]; ClockPh[ba, p, Eval]}; ClockPh: PROC[ph: QPh, p: Ports.Port, Eval: PROC [memory: BOOL _ TRUE]] = { p[ II[ PhA ].ORD ].b _ ph = A; p[ II[ PhB ].ORD ].b _ ph = B; Eval[]}; Reset: ICTest.TestProc = { p[ II[ KBus ].ORD ].lc _ 0; p[ II[ EUAluOp ].ORD ].c _ 0; p[ II[ EUCondSel ].ORD ].c _ 0; p[ II[ EUCondition ].ORD ].b _ F; p[ II[ EURdFromPBus ].ORD ].b _ F; p[ II[ EUWriteToPBus ].ORD ].b _ F; p[ II[ UserMode ].ORD ].b _ F; p[ II[ DPCmd ].ORD ].c _ 0; p[ II[ DPReject ].ORD ].b _ TRUE; p[ II[ DPFault ].ORD ].c _ 0; p[ II[ IPData ].ORD ].lc _ 0; p[ II[ IPCmdFetch ].ORD ].b _ F; p[ II[ IPReject ].ORD ].b _ TRUE; p[ II[ IPFaulting ].ORD ].b _ F; p[ II[ DShA ].ORD ].b _ F; p[ II[ DShB ].ORD ].b _ F; p[ II[ DShRd ].ORD ].b _ F; p[ II[ DShWt ].ORD ].b _ F; p[ II[ DShIn ].ORD ].b _ F; p[ II[ DShOut ].ORD ].b _ F; p[ II[ Reset ].ORD ].b _ TRUE; p[ II[ Reschedule ].ORD ].b _ F; p[ II[ KBus ].ORD ].d _ none; p[ II[ EUAluOp ].ORD ].d _ none; p[ II[ EUCondSel ].ORD ].d _ none; p[ II[ EURdFromPBus ].ORD ].d _ none; p[ II[ EUWriteToPBus ].ORD ].d _ none; p[ II[ UserMode ].ORD ].d _ none; p[ II[ DPCmd ].ORD ].d _ none; p[ II[ IPData ].ORD ].d _ none; p[ II[ IPCmdFetch ].ORD ].d _ none; p[ II[ DShOut ].ORD ].d _ none; Cycle[p, Eval]; Cycle[p, Eval]; Cycle[p, Eval]; Cycle[p, Eval]; p[ II[ Reset ].ORD ].b _ FALSE; Cycle[p, Eval]; p[ II[ KBus ].ORD ].d _ expect; p[ II[ IPData ].ORD ].d _ expect; p[ II[ EUAluOp ].ORD ].d _ expect; p[ II[ EUCondSel ].ORD ].d _ expect; p[ II[ EURdFromPBus ].ORD ].d _ expect; p[ II[ EUWriteToPBus ].ORD ].d _ expect; p[ II[ UserMode ].ORD ].d _ expect; p[ II[ DPCmd ].ORD ].d _ expect; p[ II[ IPCmdFetch ].ORD ].d _ expect; p[ II[ DShOut ].ORD ].d _ expect; p[ II[ KBus ].ORD ].lc _ 84848000H; p[ II[ DPReject ].ORD ].b _ FALSE; Cycle[p, Eval]; Cycle[p, Eval]; Cycle[p, Eval]; ClockPh[A, p, Eval]; ClockPh[ab, p, Eval]; p[ II[ IPReject ].ORD ].b _ FALSE; ClockPh[B, p, Eval]; ClockPh[ab, p, Eval]; p[ II[ EUAluOp ].ORD ].c _ Dragon.ALUOps[UAdd].ORD; p[ II[ IPCmdFetch ].ORD ].b _ TRUE; p[ II[ IPData ].ORD ].lc _ 0004041CH; ClockPh[A, p, Eval]; ClockPh[ab, p, Eval]; p[ II[ IPData ].ORD ].lc _ 0D703E400H; ClockPh[B, p, Eval]; ClockPh[ab, p, Eval]; Cycle[p, Eval]; Cycle[p, Eval]; Cycle[p, Eval]; Cycle[p, Eval]; Cycle[p, Eval]; Cycle[p, Eval]}; ICTest.RegisterTestProc[ifuChipTest, "Reset", Reset]; END. <<>> <>