IFUMainPLA:
CELL [
Interface to IFU sequence control
PreFetchFaultedBA >BOOL,
GetNextInstB <BOOL, -- iff InstReadyA
JumpB <BOOL, -- allowed any time
JumpByteOffsetB <INT[2],
P Interfaces for IFU cache
IPCmdA >EnumType["Dragon.PBusCommands"],
IPRejectB <BOOL,
IPFaultB <EnumType["Dragon.PBusFaults"],
IPNPErrorB =BOOL,
Control slice to IPCHandler
IncrPrefetchPCBA > BOOL,
Control slice to IPrefetchBuffer
IBufWrtWdClkB > INT[4],
IBufRdByteClkA > INT[16],
Control slice to IReg
BufHasAtLeast1A > BOOL, -- control slice
BufHasAtLeast2A > BOOL,
BufHasAtLeast3A > BOOL,
BufHasAtLeast5A > BOOL,
OpLengthAB < INT[3],
Serial debugging interface
All the following signals change during PhA and propagate during the remainder of PhA and PhB, giving an entire clock cycle for them to propagate throughout the machine. Each user must receive them into a latch open during PhB. The effects of changes are intended to happen throughout the following PhA, PhB pair.
DHold0BA, DHold1AB <BOOL, -- must be high before testing
Timing and housekeeping interface
PhA <BOOL,
PhB <BOOL
]
IFUSeqControl:
CELL [
Signal names obey the following convention: If a signal x is computed during PhA and remains valid throughout the following PhB, it is denoted as xAB. If x is computed during PhA and can change during the following PhB (as, for example, in precharged logic), it is denoted as xA. In this latter case, a client wanting to use x during PhB must receive it in his own latch open during PhA. xBA and xB are defined symmetrically. Positive logic is assumed (asserted = TRUE = 1 = more positive logic voltage); negative-logic signals have an extra "N" at or very near the beginning of the signal name (e.g., PNPError for PBus Negative-TRUE Parity Error).
Off-chip interface to rest of Dragon system
RescheduleAB < BOOL,
ResetAB < BOOL,
Off-chip interface to data cache's PBus
EPRejectB < BOOL,
EPFaultB < EnumType["Dragon.PBusFaults"],
Off-chip interface to EU
EUConditionBA < BOOL,
Interface to IFU main PLA
InstrDoneB < BOOL,
ALUOpB < EnumType["Dragon.ALUOps"],
CondSelect < EnumType["Dragon.CondSelects"],
TrapIfCond < BOOL,
CJumpErrIfCond < BOOL,
EUPBusCmd < EnumType["Dragon.PBusCommands"],
IsACall < BOOL,
IsAReturn < BOOL,
Interface to IFU fetch control
PreFetchFaultedBA < BOOL,
Interface to IFU stack limit test
EUStkOvflBA < BOOL,
Interface to IFU stack control
IStkEmptyA < BOOL,
IStkTooFullA < BOOL,
Interface to IFU C pipeline matcher
ARegMatchesC1A < BOOL,
ARegMatchesC2A < BOOL,
BRegMatchesC1A < BOOL,
BRegMatchesC2A < BOOL,
Serial debugging interface
All the following signals change during PhA and propagate during the remainder of PhA and PhB, giving an entire clock cycle for them to propagate throughout the machine. Each user must receive them into a latch open during PhB. The effects of changes are intended to happen throughout the following PhA, PhB pair.
DHold0BA, DHold1AB <BOOL, -- must be high before testing
Timing and housekeeping interface
PhA <BOOL,
PhB <BOOL
]
State
reschedulePending: ARRAY Dragon.Phase OF BOOL,
reset: ARRAY [0..1] OF ARRAY Dragon.Phase OF BOOL, -- shift register from ResetAB
ePRejectBA: BOOL,
instrDoneBA: BOOL,
ePFaultBA: Dragon.PBusFaults,
cycle: ARRAY Dragon.Phase OF [0..64),
condEffect: ARRAY [1..3] OF ARRAY Dragon.Phase OF {microJump, macroJump, trap},
push, pop: ARRAY [1..3] OF ARRAY Dragon.Phase OF BOOL,
EvalSimple
IF PhA
THEN
BEGIN
reset[1][a] ← reset[0][b];
END;
IF PhB
THEN
BEGIN
reset[0][b] ← ResetAB;
reset[1][b] ← reset[0][a];
ePRejectBA ← EPRejectB;
epFaultBA ← EPFaultB;
instrDoneBA ← InstrDoneB; -- IncrPCBA OR NOT NoJumpClkB
END;