[Indigo]<Dragon>IFU1Public>IFU1PublicImpl.mesa!1

IFU1PublicImpl.mesa

Don Curry January 29, 1987 1:57:00 pm PST

DIRECTORY Core, CoreCreate, CoreOps, IFU1Public, Ports, REFBit, Rosemary;

IFU1PublicImpl: CEDAR PROGRAM

IMPORTS CoreCreate, CoreOps, Ports, REFBit, Rosemary

EXPORTS IFU1Public =

BEGIN

PortWire: PUBLIC PROC

[name: Core.ROPE, size: NAT𡤀, dr: Ports.Drive←none, pwrVal: Ports.Level ← L]

RETURNS[wire: Core.Wire] = {

wire ← CoreCreate.Seq[name, (IF size=1 THEN 0 ELSE size)];

[] ← Ports.InitPort[

wire: wire,

levelType: (SELECT size FROM 0,1=>b, <=16=>c, <=32=>lc, ENDCASE=>ERROR),

initDrive: dr ];

[] ← Ports.InitTesterDrive[

wire: wire,

initDrive: (SELECT dr FROM none=>force, force, expect => none, ENDCASE=>expect)];

IF dr=infinite THEN [] ← Rosemary.SetFixedWire[wire, pwrVal]};

IfuInitializedPublic: PUBLIC PROC RETURNS[public: Core.Wire] = {

II: TYPE = IFU1Public.II;

ii: II ← LAST[II];

public ← CoreOps.CreateWires[ii.ORD+1];

public[II[KBus ].ORD] ← PortWire["KBus", 32, drive ];

public[II[EUAluOp2AB ].ORD] ← PortWire["EUAluOp2AB", 4, drive ];

public[II[EUCondSel2AB ].ORD] ← PortWire["EUCondSel2AB", 4, drive ];

public[II[EUCondition2B ].ORD] ← PortWire["EUCondition2B"];

public[II[EURdFromPBus3AB ].ORD] ← PortWire["EURdFromPBus3AB", 1, drive ];

public[II[EUWriteToPBus3AB ].ORD] ← PortWire["EUWriteToPBus3AB", 1, drive ];

public[II[UserMode2BA ].ORD] ← PortWire["UserMode2BA", 1, drive ];

public[II[DPCmdA ].ORD] ← PortWire["DPCmdA", 8, drive ];

public[II[DPRejectB ].ORD] ← PortWire["DPRejectB"];

public[II[DPFaultB ].ORD] ← PortWire["DPFaultB", 4];

public[II[IPData ].ORD] ← PortWire["IPData", 32];

public[II[IPCmdFetchA ].ORD] ← PortWire["IPCmdFetchA", 1, drive ];

public[II[IPRejectB ].ORD] ← PortWire["IPRejectB"];

public[II[IPFaultingB ].ORD] ← PortWire["IPFaultingB"];

public[II[DShA ].ORD] ← PortWire["DShA"];

public[II[DShB ].ORD] ← PortWire["DShB"];

public[II[DShRd ].ORD] ← PortWire["DShRd"];

public[II[DShWt ].ORD] ← PortWire["DShWt"];

public[II[DShIn ].ORD] ← PortWire["DShIn"];

public[II[DShOut ].ORD] ← PortWire["DShOut", 1, drive ];

public[II[ResetAB ].ORD] ← PortWire["ResetAB"];

public[II[RescheduleAB ].ORD] ← PortWire["RescheduleAB"];

public[II[PhA ].ORD] ← PortWire["PhA"];

public[II[PhB ].ORD] ← PortWire["PhB"];

public[II[NotPhA ].ORD] ← PortWire["NotPhA"];

public[II[NotPhB ].ORD] ← PortWire["NotPhB"];

public[II[IDPlaNotPhA ].ORD] ← PortWire["IDPlaNotPhA"];

public[II[Vdd ].ORD] ← PortWire["Vdd", 1, infinite, H];

public[II[Gnd ].ORD] ← PortWire["Gnd", 1, infinite, L];

public[II[PadVdd ].ORD] ← PortWire["PadVdd", 1, infinite, H];

public[II[PadGnd ].ORD] ← PortWire["PadGnd", 1, infinite, L]};

scanDrInv: PUBLIC IFU1Public.ScanRef ← ScanDrInv[];

ScanDrInv: PUBLIC PROC[scan: IFU1Public.ScanRef ← NIL] RETURNS[IFU1Public.ScanRef] = {

logicalBit: CARDINAL ← 0;

format: REFBit.Format;

IF scan=NIL THEN scan ← NEW[IFU1Public.ScanRec];

format ← REFBit.Desc[scan].fieldForm;

FOR fldFrmIdx: CARDINAL IN [0..format.size) DO -- detects Decoded Enumerated Type LSBs

field: REFBit.FormatRec ← format[fldFrmIdx];

logicalBit ← logicalBit + field.bitSize;

IF field.bitSize>1 AND

field.name=NIL AND

field.nameInv#NIL

THEN REFBit.Set[scan, logicalBit-1, NOT REFBit.Get[scan, logicalBit-1]] ENDLOOP;

scan.MPOut.notBcLoadStage1 ← NOT scan.MPOut.notBcLoadStage1;

scan.FCOut.notInstReady ← NOT scan.FCOut.notInstReady;

RETURN[scan]};

SetScanBit: PUBLIC PROC[scan: IFU1Public.ScanRef, bit: NAT, val: BOOL] = {

inv: BOOL ← REFBit.Get[scanDrInv, bit];

REFBit.Set[scan, bit, val#inv]};

GetScanBit: PUBLIC PROC[scan: IFU1Public.ScanRef, bit: NAT] RETURNS[ val: BOOL] = {

inv: BOOL ← REFBit.Get[scanDrInv, bit];

val ← inv#REFBit.Get[scan, bit]};

END.