Dragon1.mesa
Copyright © 1986 by Xerox Corporation. All rights reserved.
Modified for Core and Rosemary5
Auxiliary functions for Dragon Rosemary simulations
last edited by E. McCreight, September 10, 1986 5:14:51 pm PDT
last edited by TWilliams, August 6, 1984 4:14:53 pm PDT
last edited by Curry, September 11, 1986 0:18:10 am PDT
Don Curry April 2, 1987 5:51:04 pm PST
DIRECTORY DragOpsCross1;
Dragon1: CEDAR DEFINITIONS =
BEGIN
-- Dragon -- Word: TYPE = LONG CARDINAL;
HexNibble:   TYPE = [0..16); -- forces hexadecimal ViewRec
HexByte:    TYPE = Byte;  -- forces hexadecimal ViewRec
HexWord:    TYPE = Word; -- forces hexadecimal ViewRec
Byte:     TYPE = [0..256);
Opcode:    TYPE = HexByte;
EURegisterIndex: TYPE = [0..256);
SLRange:    TYPE = EURegisterIndex[0..128);
Phase:     TYPE = MACHINE DEPENDENT {a(0), b(1)};
Cycle:     TYPE = NAT;
UndefinedValue: Dragon1.HexWord = 01234567H;
ALUOps: TYPE = MACHINE DEPENDENT {
Or(0),    And(1),   VAdd2(2),  BndChk(3),
SAdd(4),   SSub(5),   LAdd(6),   LSub(7),
Xor(8),   res9(9),   FOP(10),   res11(11),
VAdd(12),  VSub(13),  UAdd(14),  USub(15) };
aluOpSig: ALUOps = LOOPHOLE[15];
CondSelects: TYPE = MACHINE DEPENDENT {
False   (DragOpsCross1.TrapIndex[ ALUCondFalse ].ORD MOD 16),
EZ    (DragOpsCross1.TrapIndex[ ALUCondEZ  ].ORD MOD 16),
LZ    (DragOpsCross1.TrapIndex[ ALUCondLZ  ].ORD MOD 16),
LE    (DragOpsCross1.TrapIndex[ ALUCondLE  ].ORD MOD 16),
res4   (DragOpsCross1.TrapIndex[ ALUCondSpare ].ORD MOD 16),
NE   (DragOpsCross1.TrapIndex[ ALUCondNE  ].ORD MOD 16),
GE    (DragOpsCross1.TrapIndex[ ALUCondGE  ].ORD MOD 16),
GZ    (DragOpsCross1.TrapIndex[ ALUCondGZ  ].ORD MOD 16),
OvFl   (DragOpsCross1.TrapIndex[ ALUCondOver ].ORD MOD 16),
BC    (DragOpsCross1.TrapIndex[ ALUCondBC  ].ORD MOD 16),
IL    (DragOpsCross1.TrapIndex[ ALUCondIL  ].ORD MOD 16),
res11   (DragOpsCross1.TrapIndex[ ALUCondDO  ].ORD MOD 16),
res12   (DragOpsCross1.TrapIndex[ ALUCondNotOver ].ORD MOD 16),
NotBC   (DragOpsCross1.TrapIndex[ ALUCondNB  ].ORD MOD 16),
NotIL   (DragOpsCross1.TrapIndex[ ALUCondNI  ].ORD MOD 16),
ModeFault (DragOpsCross1.TrapIndex[ ModeFault   ].ORD MOD 16) };
ALULeftSources:  TYPE = MACHINE DEPENDENT {aBus(0), rBus(1), cBus(2), reserve3(3)};
ALURightSources: TYPE = MACHINE DEPENDENT
{bBus(0), rBus(1), cBus(2), kBus(3), fCtlReg(4), reserve5(5), reserve6(6), reserve7(7)};
Store2ASources:  TYPE = MACHINE DEPENDENT {bBus(0), rBus(1), cBus(2), reserve3(3)};
rd: [0..256) = 0;
wrt: [0..256) = 1;
basicCache: [0..256) = 128;
io: [0..256) = 4;
special: [0..256) = 2;
byte0: [0..256) = 64;
byte1: [0..256) = 32;
byte2: [0..256) = 16;
byte3: [0..256) = 8;
allBytes: [0..256) = 120;
cache: [0..256) = basicCache+allBytes;
au: [0..256) = 2*deviceMult;
fn: [0..256) = 8;
auLt: [0..256) = au+0;
auLtx: [0..256) = au+16;
auRt: [0..256) = au+32;
auRtx: [0..256) = au+48;
auMF: [0..256) = au+64;
auLtRt: [0..256) = au+80;
auRsLt: [0..256) = au+96;
auRsRt: [0..256) = au+108;
PBusCommands: TYPE = MACHINE DEPENDENT {
NoOp(0),
Fetch(cache+rd),      Store(cache+wrt),
FetchSpecial(cache+special+rd),
IOFetch(cache+io+rd),     IOStore(cache+io+wrt),
           IOStoreSpecial(cache+io+special+wrt) };
AUFetchLt(auLt+rd),     AUStoreLt(auLt+wrt),
AUFetchLtFn(auLt+fn+rd),   AUStoreLtFn(auLt+fn+wrt),
AUFetchLtx(auLtx+rd),    AUStoreLtx(auLtx+wrt),
AUFetchLtxFn(auLtx+fn+rd),
AUFetchRt(auRt+rd),     AUStoreRt(auRt+wrt),
AUFetchRtFn(auRt+fn+rd),   AUStoreRtFn(auRt+fn+wrt),
AUFetchRtx(auRtx+rd),    AUStoreRtx(auRtx+wrt),
AUFetchRtxFn(auRtx+fn+rd),
AUFetchMF(auMF+rd),    AUStoreMF(auMF+wrt),
AUFetchMFFn(auMF+fn+rd),  AUStoreMFFn(auMF+fn+wrt),
           AUStoreLtRt(auLtRt+wrt),
AUFetchRslt(auRsLt+rd),    AUXferToLtx(auRsLt+wrt),
AUFetchRsltFn(auRsLt+fn+rd),  AUXferToLtxFn(auRsLt+fn+wrt),
AUFetchRsltx(auRsRt+rd),    AUXferToRtx(auRsRt+wrt),
AUFetchRsltxFn(auRsRt+fn+rd),  AUXferToRtxFn(auRsRt+fn+wrt),
PBusFaultCode: TYPE = MACHINE DEPENDENT {
memAccess ((DragOpsCross1.TrapIndex[ MemAccessFault ].ORD MOD 8)),
ioAccess  ((DragOpsCross1.TrapIndex[ IOAccessFault  ].ORD MOD 8)),
page   ((DragOpsCross1.TrapIndex[ EUPageFault  ].ORD MOD 8)),
write   ((DragOpsCross1.TrapIndex[ EUWriteFault  ].ORD MOD 8)),
arithmetic ((DragOpsCross1.TrapIndex[ AUFault    ].ORD MOD 8)) };
PBusFaults: TYPE = MACHINE DEPENDENT {
none   (0),
memAccess (8+(DragOpsCross1.TrapIndex[ MemAccessFault  ].ORD MOD 8)),
ioAccess  (8+(DragOpsCross1.TrapIndex[ IOAccessFault  ].ORD MOD 8)),
page   (8+(DragOpsCross1.TrapIndex[ EUPageFault   ].ORD MOD 8)),
write   (8+(DragOpsCross1.TrapIndex[ EUWriteFault  ].ORD MOD 8)),
arithmetic (8+(DragOpsCross1.TrapIndex[ AUFault    ].ORD MOD 8)) };
Position of a microinstruction's a, b, and c register addresses on the KBus between the IFU and EU during its clock phases 1B, 1B, and 3B, respectively.
aRegKBusPos: [0..32) = 0; -- high-order 8 bits of KBus
bRegKBusPos: [0..32) = 8;
cRegKBusPos: [0..32) = 16;
Record types for comparing simulations
CacheTrans: TYPE = REF CacheTransRec;
CacheTransRec: TYPE = RECORD [
instr: INT,
cmd: Dragon1.PBusCommands,
addr, data: Dragon1.Word,
fault: Dragon1.PBusFaults
];
RegStore: TYPE = REF RegStoreRec;
RegStoreRec: TYPE = RECORD [
instr: INT,
reg: DragOpsCross1.ProcessorRegister,
data: Dragon1.Word
];
END.