IFUCorrections.tioga

X's in Adder outputs caused by disconnected carry ins. Overlayed conditional objects.

X's in IPFetch. Pad gate - open in layout.

CoreFlat - (wire type none - interchange lines)

Rosemary, charge problem caused X's.

RetchRd index - Mux input wrong

LoadStage1Bc - Driver inverted

Tristate Pads - control transistor needs to be next to pad - probably no serious problem.

Drivers inverted - Debug controls

Pad Extraction incorrect for overlapping cells (Gates)

Pads redone

IPData - Pad Proc arguments reversed (in/out) pad = (out/in) chip

UserMode - unnecessarily gating, there to be consistant with DPCmd, removed

PreCharge Eval Proc - driver ← none when control false

Missing NotDPReject - (Need static check for nodes w/ no channel)

Wrong name used to build Formal cell (Pad-IPAddr > Pad-IPData)

DpDisChg - Clock must be next to GND in Discharge cells (ABCompare problem)

Missing '.' in IFUSrcFetch.FetchMuxB FetchAddrAB.

CRegOffSet.0 => NotCRegOffSet.0

Removed Inverter after FetchBuf

Grounded Dummy in StackBuf

Added drive control (=none) to StackBuf and FetchBuf Eval Procs

Added fire/fireV/nPC to PLA Desc and Drive records

LSForm FlagB mux input was GND. (had period)

Fetch decoders were upside down

routing of IDFireV and IDNotPhA at bottom of right column

missing '.' in XaPipeB0.30..37 Mux

defualt Port init is b => unused signal (DisChg) = X causes problem

init Stack to 0

PCFormTop - Sign extend Alpha and Beta NOT 7 but 0!

PushBA unintentional bind inside StackBControl (driver/pla body nameing, in/out same name)

A and B sign extend offsets

Data and control switched DpLatchCtl

DpLatch-G-= and DpLatch-V-= Eval Procs Aliased

Remove S from IFU Stack (can easily add back in)

Large Mux for LSForm had SBA and LBA (which were unrouted) rather than SAB and LAB

IFU2Impl IPFaultingBA ← p[II[IPFaultingB].ORD].b (was p[II[..].ORD].c = page fault)

ABForm StateAB - use PHA not LoadStage1Ac

Pruned TrapTest into Quick Test

Ran first part ~ 350 cycles

Remade IFUCore drivers, symetric, no DRC problems (expect no well contact where its in next cell)

Rebuilt everything using NewCore, Rosemary etc, Made new checkpoints